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74LVC1G80GW PDF даташит

Спецификация 74LVC1G80GW изготовлена ​​​​«Panasonic Semiconductor» и имеет функцию, называемую «Single D-type flip-flop; positive-edge trigger».

Детали детали

Номер произв 74LVC1G80GW
Описание Single D-type flip-flop; positive-edge trigger
Производители Panasonic Semiconductor
логотип Panasonic Semiconductor логотип 

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74LVC1G80GW Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G80
Single D-type flip-flop;
positive-edge trigger
Product specification
Supersedes data of 2004 Jun 29
2004 Sep 10









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74LVC1G80GW Даташит, Описание, Даташиты
Philips Semiconductors
Single D-type flip-flop; positive-edge trigger
Product specification
74LVC1G80
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 °C to +85 °C and
40 °C to +125 °C.
DESCRIPTION
The 74LVC1G80 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This
feature allows the use of this device in a mixed
3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G80 provides a single positive-edge triggered
D-type flip-flop.
Information on the data input is transferred to the Q output
pin on the LOW-to-HIGH transition of the clock pulse.
The input pin D must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay CP to Q
fmax maximum frequency
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 5.0 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.4 ns
2.3 ns
2.5 ns
2.4 ns
1.8 ns
350 MHz
5.0 pF
17 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2004 Sep 10
2









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74LVC1G80GW Даташит, Описание, Даташиты
Philips Semiconductors
Single D-type flip-flop; positive-edge trigger
Product specification
74LVC1G80
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
CP D
L
H
LX
Q
H
L
q
Note
1. H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
ORDERING INFORMATION
TYPE NUMBER
74LVC1G80GW
74LVC1G80GV
74LVC1G80GM
TEMPERATURE
RANGE
40 °C to +125 °C
40 °C to +125 °C
40 °C to +125 °C
PINS
5
5
6
PACKAGE
PACKAGE MATERIAL CODE MARKING
SC-88A
SC-74A
XSON6
plastic
plastic
plastic
SOT353-1
SOT753
SOT886
VT
V80
VT
PINNING
PIN TSSOP5; SC-74A
1
2
3
4
-
5
PIN XSON6
1
2
3
4
5
6
SYMBOL
D
CP
GND
Q
n.c.
VCC
DESCRIPTION
input D
clock pulse input CP
ground (0 V)
output Q
not connected
supply voltage
2004 Sep 10
3










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Номер в каталогеОписаниеПроизводители
74LVC1G80GMSingle D-type flip-flop; positive-edge triggerPanasonic Semiconductor
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74LVC1G80GVSingle D-type flip-flop; positive-edge triggerPanasonic Semiconductor
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74LVC1G80GWSingle D-type flip-flop; positive-edge triggerPanasonic Semiconductor
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