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74LVC240 PDF даташит

Спецификация 74LVC240 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting 3-State».

Детали детали

Номер произв 74LVC240
Описание Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC240 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LVC240A
Octal buffer/line driver with 5-volt tolerant
inputs/outputs; inverting (3-State)
Product specification
IC24 Data Handbook
1998 May 20
Philips
Semiconductors









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74LVC240 Даташит, Описание, Даташиты
Philips Semiconductors
Octal buffer/line driver with 5-volt
tolerant inputs/outputs; inverting (3-State)
Product specification
74LVC240A
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
High impedance when VCC = 0V
DESCRIPTION
The 74LVC240A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. These features allow the use of
these devices as translators in a mixed 3.3V/5V environment.
The ‘240A is an octal non-inverting buffer/line driver with 3-State
outputs. The 3-State outputs are controlled by the output enable
inputs 1OE and 2OE. A HIGH on nOE causes the outputs to
assume a high impedance OFF-state. Schmitt-trigger action at all
inputs makes the circuit highly tolerant for slower input rise and fall
times.
The ’240’ is functionally identical to the ’244’, but the ’244’ has
inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
1An to 1Yn;
2An to 2Yn
CL = 50pF
VCC = 3.3V
CI Input capacitance
CPD
Power dissipation capacitance per
buffer
Notes 1 and 2
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL x VCC2 x fo) = sum of outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Small Outline (SO)
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
TEMPERATURE
OUTSIDE
RANGE
NORTH AMERICA
–40°C to +85°C 74LVC240A D
–40°C to +85°C 74LVC240A DB
–40°C to +85°C 74LVC240A PW
TYPICAL
3.5
5.0
20
NORTH AMERICA
74LVC240A D
74LVC240A DB
7LVC240APW DH
UNIT
ns
pF
pF
PKG. DWG. #
SOT163-1
SOT339-1
SOT360-1
1998 May 20
2 853-1981 19419









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74LVC240 Даташит, Описание, Даташиты
Philips Semiconductors
Octal buffer/line driver with 5-volt
tolerant inputs/outputs; inverting (3-State)
Product specification
74LVC240A
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1
2, 4, 6, 8
3, 5, 7, 9
10
1OE
1A0 to 1A3
2Y0 to 2Y3
GND
Output enable input (active LOW)
Data inputs
Bus outputs
Ground (0V)
17, 15, 13, 11
18, 16, 14, 12
19
2A0 to 2A3
1Y0 to 1Y3
2OE
Bus inputs
Bus outputs
Output enable input (active-LOW)
20 VCC Positive power supply
PIN CONFIGURATION
1OE 1
1A0 2
2Y0 3
1A1 4
2Y1 5
1A2 6
2Y2 7
1A3 8
2Y3 9
GND 10
20 VCC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
SV00212
LOGIC SYMBOL (IEEE/IEC)
1
EN
2
4
6
8
18
16
14
12
19
EN
11
13
15
17
9
7
5
3
SV00611
FUNCTION TABLE
INPUTS
nOE
L
nAn
L
LH
HX
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance OFF-state
LOGIC SYMBOL
2 1A 0
17 2A 0
4 1A 1
15 2A 1
6 1A 2
13 2A 2
8 1A 3
11 2A 3
1 1OE
19 2OE
OUTPUT
nYn
H
L
Z
1Y 0 18
2Y 0 3
1Y 1 16
2Y 1 5
1Y 2 14
2Y 2 7
1Y 3 12
2Y 3 9
SV00608
FUNCTIONAL DIAGRAM
2 1A 0
4 1A 1
6 1A 2
8 1A 3
1 1OE
17 2A 0
15 2A 1
13 2A 2
11 2A 3
19 2OE
1Y 0 18
1Y 1 16
1Y 2 14
1Y 3 12
2Y 0 3
2Y 1 5
2Y 2 7
2Y 3 9
SV00610
1998 May 20
3










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