74LVC2G00 PDF даташит
Спецификация 74LVC2G00 изготовлена «Panasonic Semiconductor» и имеет функцию, называемую «Dual 2-input NAND gate». |
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Детали детали
Номер произв | 74LVC2G00 |
Описание | Dual 2-input NAND gate |
Производители | Panasonic Semiconductor |
логотип |
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INTEGRATED CIRCUITS
DATA SHEET
74LVC2G00
Dual 2-input NAND gate
Product specification
Supersedes data of 2003 Nov 17
2004 Sep 23
No Preview Available ! |
Philips Semiconductors
Dual 2-input NAND gate
Product specification
74LVC2G00
FEATURES
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant outputs for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74LVC2G00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
These feature allows the use of these devices as
translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G00 provides the 2-input NAND gate.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
tPHL/tPLH
CI
CPD
PARAMETER
CONDITIONS
propagation delay
inputs nA, nB to output nY
input capacitance
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω
power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.5 ns
2.3 ns
3.0 ns
2.2 ns
1.8 ns
2.5 pF
14 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2004 Sep 23
2
No Preview Available ! |
Philips Semiconductors
Dual 2-input NAND gate
Product specification
74LVC2G00
FUNCTION TABLE
See note 1.
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
INPUT
nB
L
H
L
H
OUTPUT
nY
H
H
H
L
ORDERING INFORMATION
TYPE NUMBER
74LVC2G00DP
74LVC2G00DC
74LVC2G00DM
TEMPERATURE
RANGE
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
PINS
8
8
8
PACKAGE
PACKAGE
TSSOP8
VSSOP8
XSON8
MATERIAL
plastic
plastic
plastic
CODE
SOT505-2
SOT765-1
SOT833-1
MARKING
V00
V00
V00
PINNING
PIN
1
2
3
4
5
6
7
8
SYMBOL
1A
1B
2Y
GND
2A
2B
1Y
VCC
data input 1A
data input 1B
data output 2Y
ground (0 V)
data input 2A
data input 2B
data output 1Y
supply voltage
DESCRIPTION
2004 Sep 23
3
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Номер в каталоге | Описание | Производители |
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