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74LVC2G04GM PDF даташит

Спецификация 74LVC2G04GM изготовлена ​​​​«Panasonic Semiconductor» и имеет функцию, называемую «Dual inverter».

Детали детали

Номер произв 74LVC2G04GM
Описание Dual inverter
Производители Panasonic Semiconductor
логотип Panasonic Semiconductor логотип 

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74LVC2G04GM Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74LVC2G04
Dual inverter
Product specification
Supersedes data of 2003 Jul 22
2004 Sep 15









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74LVC2G04GM Даташит, Описание, Даташиты
Philips Semiconductors
Dual inverter
Product specification
74LVC2G04
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from 40 °C to +85 °C and
40 °C to +125 °C.
DESCRIPTION
The 74LVC2G04 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
These feature allows the use of these devices as
translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G04 provides two inverting buffers.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
tPHL/tPLH
CI
CPD
PARAMETER
propagation delay inputs nA to
outputs nY
input capacitance
power dissipation capacitance per gate
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 5.0 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.5 ns
2.2 ns
2.7 ns
2.7 ns
1.9 ns
2.5 pF
13.5 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
2004 Sep 15
2









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74LVC2G04GM Даташит, Описание, Даташиты
Philips Semiconductors
Dual inverter
Product specification
74LVC2G04
FUNCTION TABLE
See note 1.
INPUT
nA
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
OUTPUT
nY
H
L
ORDERING INFORMATION
TYPE NUMBER
74LVC2G04GW
74LVC2G04GV
74LVC2G04GM
TEMPERATURE RANGE
40 °C to +125 °C
40 °C to +125 °C
40 °C to +125 °C
PINS
6
6
6
PACKAGE
PACKAGE MATERIAL
SC-88
plastic
SC-74
plastic
XSON6
plastic
CODE
SOT363
SOT457
SOT886
MARKING
V4
V04
V4
PINNING
PIN
1
2
3
4
5
6
1A
GND
2A
2Y
VCC
1Y
SYMBOL
data input
ground (0 V)
data input
data output
supply voltage
data output
DESCRIPTION
1A 1
GND 2
2A 3
6 1Y
04 5 VCC
4 2Y
001aab649
Fig.1 Pin configuration SC-88 and SC-74.
2004 Sep 15
3
04
1A 1
6 1Y
GND 2
5 VCC
2A 3
4 2Y
001aab650
Transparent top view
Fig.2 Pin configuration XSON6.










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Номер в каталогеОписаниеПроизводители
74LVC2G04GMDual inverterPanasonic Semiconductor
Panasonic Semiconductor
74LVC2G04GVDual inverterPanasonic Semiconductor
Panasonic Semiconductor
74LVC2G04GWDual inverterPanasonic Semiconductor
Panasonic Semiconductor

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