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PDF 74LVC2G125 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G125 | |
| Descripción | Dual bus buffer/line driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVC2G125
Dual bus buffer/line driver; 3-state
Rev. 14 — 29 March 2013
Product data sheet
1. General description
The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24 mA output drive (VCC = 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
1 page  
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
0.5 +6.5 V
IIK input clamping current VI < 0 V
50 -
mA
VI input voltage
[1] 0.5
+6.5
V
IOK output clamping current VO > VCC or VO < 0 V
- 50 mA
VO
output voltage
Enable mode
[1] 0.5
VCC + 0.5 V
Disable mode
[1] 0.5
+6.5
V
Power-down mode
[1][2] 0.5
+6.5
V
IO
output current
VO = 0 V to VCC
- 50 mA
ICC
IGND
supply current
ground current
-
100
100
-
mA
mA
Tstg storage temperature
65
+150
C
Ptot
total power dissipation Tamb = 40 C to +125 C
[3] -
300 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8, XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
VI
VO
Tamb
t/V
Operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
ambient temperature
VCC = 1.65 V to 5.5 V; Enable mode
VCC = 1.65 V to 5.5 V; Disable mode
VCC = 0 V; Power-down mode
input transition rise and VCC = 1.65 V to 2.7 V
fall rate
VCC = 2.7 V to 5.5 V
Min Max Unit
1.65 5.5
V
0 5.5 V
0
VCC
V
0 5.5 V
0 5.5 V
40
+125
C
- 20 ns/V
- 10 ns/V
74LVC2G125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 14 — 29 March 2013
© NXP B.V. 2013. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
13. Package outline
74LVC2G125
Dual bus buffer/line driver; 3-state
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
y
Z
8
5
c
EA
X
HE v M A
pin 1 index
1
e
4
bp w M
A A2
A1
(A3)
detail X
Lp
L
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c D(1) E(1) e
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
HE
4.1
3.9
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT505-2
---
L Lp v w y Z(1)
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
θ
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
Fig 10. Package outline SOT505-2 (TSSOP8)
74LVC2G125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 14 — 29 March 2013
© NXP B.V. 2013. All rights reserved.
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| PDF Descargar | [ Datasheet 74LVC2G125.PDF ] | |
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