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74LVC2G126GM PDF даташит

Спецификация 74LVC2G126GM изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Dual bus buffer/line driver; 3-state».

Детали детали

Номер произв 74LVC2G126GM
Описание Dual bus buffer/line driver; 3-state
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC2G126GM Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74LVC2G126
Dual bus buffer/line driver; 3-state
Product specification
Supersedes data of 2003 Sep 01
2004 Sep 22









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74LVC2G126GM Даташит, Описание, Даташиты
Philips Semiconductors
Dual bus buffer/line driver; 3-state
Product specification
74LVC2G126
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 °C to +85 °C and 40 °C to +125 °C.
DESCRIPTION
The 74LVC2G126 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
These feature allows the use of these devices as
translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G126 provides a dual non-inverting buffer/line
driver with 3-state output. The 3-state output is controlled
by the output enable input (pin nOE). A LOW-level at
pin nOE causes the output to assume a high-impedance
OFF-state. Schmitt-trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL UNIT
tPHL/tPLH
CI
CPD
propagation delay inputs nA to output nY VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 5.0 V; CL = 50 pF; RL = 500
input capacitance
power dissipation capacitance per buffer output enabled; notes 1 and 2
output disabled; notes 1 and 2
3.9
2.6
2.8
2.4
1.9
2
17
5
ns
ns
ns
ns
ns
pF
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
2004 Sep 22
2









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74LVC2G126GM Даташит, Описание, Даташиты
Philips Semiconductors
Dual bus buffer/line driver; 3-state
Product specification
74LVC2G126
FUNCTION TABLE
See note 1.
INPUT
nOE
H
H
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
nA
L
H
X
OUTPUT
nY
L
H
Z
ORDERING INFORMATION
TYPE NUMBER
74LVC2G126DP
74LVC2G126DC
74LVC2G126GM
TEMPERATURE
RANGE
40 °C to +125 °C
40 °C to +125 °C
40 °C to +125 °C
PINS
8
8
8
PACKAGE
PACKAGE
TSSOP8
VSSOP8
XSON8
MATERIAL
plastic
plastic
plastic
CODE
SOT505-2
SOT765-1
SOT833-1
MARKING
V126
V26
V26
PINNING
PIN
1
2
3
4
5
6
7
8
SYMBOL
1OE
1A
2Y
GND
2A
1Y
2OE
VCC
output enable input
data input
data output
ground (0 V)
data input
data output
output enable input
supply voltage
DESCRIPTION
2004 Sep 22
3










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74LVC2G126GMDual bus buffer/line driver; 3-stateNXP Semiconductors
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