74LVC2G14GW PDF даташит
Спецификация 74LVC2G14GW изготовлена «NXP Semiconductors» и имеет функцию, называемую «Dual inverting Schmitt-trigger with 5 V tolerant input». |
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Детали детали
Номер произв | 74LVC2G14GW |
Описание | Dual inverting Schmitt-trigger with 5 V tolerant input |
Производители | NXP Semiconductors |
логотип |
17 Pages
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INTEGRATED CIRCUITS
DATA SHEET
74LVC2G14
Dual inverting Schmitt-trigger with
5 V tolerant input
Product specification
Supersedes data of 2003 Jul 31
2004 Sep 08
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Philips Semiconductors
Dual inverting Schmitt-trigger with
5 V tolerant input
Product specification
74LVC2G14
FEATURES
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant input/output for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Mulltiple package options
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and
−40 °C to +125 °C.
APPLICATIONS
• Wave and pulse shapers for highly noisy environments
• Astable multivibrators
• Monostable multivibrators.
DESCRIPTION
The 74LVC2G14 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This
feature allows the use of this device as translator in a
mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G14A provides two inverting buffers with
Schmitt-trigger action. It is capable of transforming slowly
changing input signals into sharply defined, jitter-free
output signals.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C
SYMBOL
tPHL/tPLH
CI
CPD
PARAMETER
propagation delay input nA to output nY
input capacitance
power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; notes 1 and 2
TYPICAL
5.6
3.7
4.1
3.9
2.7
3.5
18.1
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
∑(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
UNIT
ns
ns
ns
ns
ns
pF
pF
2004 Sep 08
2
No Preview Available ! |
Philips Semiconductors
Dual inverting Schmitt-trigger with
5 V tolerant input
Product specification
74LVC2G14
FUNCTION TABLE
See note 1.
INPUT
nA
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
OUTPUT
nY
H
L
ORDERING INFORMATION
TYPE NUMBER
74LVC2G14GW
74LVC2G14GV
74LVC2G14GM
TEMPERATURE RANGE
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
PINS
6
6
6
PACKAGE
PACKAGE
SC-88
SC-74
XSON6
MATERIAL
plastic
plastic
plastic
CODE
SOT363
SOT457
SOT886
MARKING
VK
V14
VK
PINNING
PIN
1
2
3
4
5
6
1A
GND
2A
2Y
VCC
1Y
SYMBOL
data input
ground (0 V)
data input
data output
supply voltage
data output
DESCRIPTION
1A 1
GND 2
2A 3
6 1Y
14 5 VCC
4 2Y
001aab672
Fig.1 Pin configuration SC-88 and SC-74.
2004 Sep 08
3
14
1A 1
6 1Y
GND 2
5 VCC
2A 3
4 2Y
001aab673
Transparent top view
Fig.2 Pin configuration XSON6.
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Номер в каталоге | Описание | Производители |
74LVC2G14GM | Dual inverting Schmitt-trigger with 5 V tolerant input | NXP Semiconductors |
74LVC2G14GV | Dual inverting Schmitt-trigger with 5 V tolerant input | NXP Semiconductors |
74LVC2G14GW | Dual inverting Schmitt-trigger with 5 V tolerant input | NXP Semiconductors |
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