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74LVC4066PW PDF даташит

Спецификация 74LVC4066PW изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Quad bilateral switches».

Детали детали

Номер произв 74LVC4066PW
Описание Quad bilateral switches
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC4066PW Даташит, Описание, Даташиты
74LVC4066
Quad bilateral switch
Rev. 5 — 23 November 2011
Product data sheet
1. General description
The 74LVC4066 is a high-speed Si-gate CMOS device.
The 74LVC4066 provides four single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 (typical) at VCC = 2.7 V
6.5 (typical) at VCC = 3.3 V
6 (typical) at VCC = 5 V
Switch current capability of 32 mA
High noise immunity
CMOS low-power consumption
Direct interface TTL-levels
Latch-up performance exceeds 250 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Enable inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C









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74LVC4066PW Даташит, Описание, Даташиты
NXP Semiconductors
74LVC4066
Quad bilateral switch
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC4066D 40 C to +125 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC4066PW 40 C to +125 C TSSOP14 plastic thin small outline package; 14 leads;
body width 4.4 mm
74LVC4066BQ 40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
4. Functional diagram
1 1Y
13 1E
4 2Y
5 2E
8 3Y
6 3E
11 4Y
12 4E
Fig 1. Logic symbol
1Z 2
2Z 3
3Z 9
4Z 10
mnb111
nY
nE
Fig 3. Logic diagram (one switch)
1
13 #
4
5#
8
6#
11
12 #
2
3
9
10
(a)
11
13 # X1
12
41
5 # X1
13
81
6 # X1
19
11 1
12 # X1
1 10
(b)
mnb112
Fig 2. Logic symbol (IEEE/IEC)
nZ
VCC
mna658
74LVC4066
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 23 November 2011
© NXP B.V. 2011. All rights reserved.
2 of 23









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74LVC4066PW Даташит, Описание, Даташиты
NXP Semiconductors
5. Pinning information
5.1 Pinning
74LVC4066
Quad bilateral switch
1Y 1
1Z 2
2Z 3
2Y 4
2E 5
3E 6
GND 7
14 VCC
13 1E
12 4E
4066
11 4Y
10 4Z
9 3Z
8 3Y
001aad117
Fig 4. Pin configuration for SO14 and TSSOP14
terminal 1
index area
1Z 2
2Z 3
2Y 4
2E 5
3E 6
4066
GND(1)
13 1E
12 4E
11 4Y
10 4Z
9 3Z
001aad118
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y
1Z
2Z
2Y
2E
3E
GND
3Y
3Z
4Z
4Y
4E
1E
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
independent input/output
independent output/input
independent output/input
independent input/output
enable input (active HIGH)
enable input (active HIGH)
ground (0 V)
independent input/output
independent output/input
independent output/input
independent input/output
enable input (active HIGH)
enable input (active HIGH)
supply voltage
74LVC4066
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 23 November 2011
© NXP B.V. 2011. All rights reserved.
3 of 23










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74LVC4066PWQuad bilateral switchesNXP Semiconductors
NXP Semiconductors

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