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74LVC544APW PDF даташит

Спецификация 74LVC544APW изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Octal D-type registered transceiver/ inverting 3-State».

Детали детали

Номер произв 74LVC544APW
Описание Octal D-type registered transceiver/ inverting 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC544APW Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LVC544A
Octal D-type registered transceiver,
inverting (3-State)
Product specification
1998 Jul 29
Philips
Semiconductors









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74LVC544APW Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type registered transceiver, inverting
(3-State)
Product specification
74LVC544A
FEATURES
Wide supply voltage range of 1.2V to 3.6V
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
Combines 74LVC640 and 74LVC533 type functions in one chip
Octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-State inverting outputs for bus oriented applications
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC544A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC544A is an octal registered inverting transceiver
containing two sets of D-type latches for temporary storage of the
data flow in either direction. Separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) inputs are provided for each
register to permit independent control of inputting and outputting in
either direction of the data flow.
The ‘544A’ contains eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for example, the
A-to-B enable (EAB) input must be LOW in order to enter data from
A0–A7 or take data from B0–B7, as indicated in the function table.
With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB)
input makes the A-to-B latches transparent; a subsequent
LOW-to-HIGH transition of the LEAB signal puts the A data into the
latches where it is stored and the B outputs no longer change with
the A inputs. With EAB and OEAB both LOW, the 3-State B output
buffers are active and display the data present at the outputs of the
A latches.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
An to Bn
CL = 50pF
VCC = 3.3V
CI Input capacitance
CI/O Input/output capacitance
CPD Power dissipation capacitance per latch Notes 1, 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi )Σ (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
4
5.0
10
30
UNIT
ns
pF
pF
pF
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
24-Pin Plastic SO
–40°C to +85°C
OUTSIDE NORTH
AMERICA
74LVC544A D
NORTH AMERICA
74LVC544A D
PKG. DWG. #
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
–40°C to +85°C
–40°C to +85°C
74LVC544A DB
74LVC544A PW
74LVC544A DB
7LVC544APW DH
SOT340-1
SOT355-1
1998 Jul 29
2 853-2107 19804









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74LVC544APW Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type registered transceiver, inverting
(3-State)
Product specification
74LVC544A
PIN DESCRIPTION
PIN NUMBER SYMBOL
1 LEBA
2 OEBA
3, 4, 5, 6,
7, 8, 9, 10
11
12
22, 21, 20, 19,
18, 17, 16, 15
A0–A7
EBA
GND
B0–B7
13 OEAB
14 LEAB
23 EAB
24 VCC
FUNCTION
‘B’ to ‘A’ latch enable input (active
LOW)
‘B’ to ‘A’ output enable input (active
LOW)
‘A’ data inputs/outputs
‘B’ to ‘A’ enable input (active LOW)
Ground (0V)
‘B’ data inputs/outputs
‘A’ to ‘B’ output enable input (active
LOW)
‘A’ to ‘B’ latch enable input (active
LOW)
‘A’ to ‘B’ enable input (active LOW)
Positive supply voltage
PIN CONFIGURATION
LEBA 1
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND 12
24 VCC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
SV00733
FUNCTION TABLE
OEXX
EXX
INPUTS
LEXX
DATA
OUTPUTS
HXXXZ
XHXXZ
LLhZ
LL l Z
LLhL
LLl H
L L LHL
L L L LH
L L H X NC
XX = AB for A-to-B direction, BA for B-to-A direction
H = HIGH voltage level
L = LOW voltage level
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA
X = Don’t care
= LOW–to–HIGH level transition
NC = No change
Z = High impedance OFF-state
STATUS
Disabled
Disabled
Disabled + Latch
Latch + Display
Transparent
Hold
1998 Jul 29
3










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