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74LVC573A PDF даташит

Спецификация 74LVC573A изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Octal D-type transparent latch».

Детали детали

Номер произв 74LVC573A
Описание Octal D-type transparent latch
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC573A Даташит, Описание, Даташиты
74LVC573A
Octal D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 5 — 19 February 2013
Product data sheet
1. General description
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are common to all internal latches.
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches
are transparent, that is, a latch output changes each time its corresponding D-input
changes. When LE is LOW, the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs. When OE
is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does
not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V or 5 V applications.
The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin
arrangement.
2. Features and benefits
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when VCC = 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C









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74LVC573A Даташит, Описание, Даташиты
NXP Semiconductors
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC573AD 40 C to +125 C SO20
plastic small outline package; 20 leads;
body width 7.5 mm
74LVC573ADB 40 C to +125 C SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
74LVC573APW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
74LVC573ABQ 40 C to +125 C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
74LVC573ABX 40 C to +125 C
DHXQFN20 plastic dual in-line compatible thermal enhanced
extremely thin quad flat package; no leads; 20
terminals; body 4.5 2.5 0.5 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
SOT1045-2
4. Functional diagram
1
OE
2 D0
Q0 19
3 D1
Q1 18
4 D2
Q2 17
5 D3
Q3 16
6 D4
15
Q4
7 D5
14
Q5
8
D6
13
Q6
9
D7
12
Q7
LE
11 mna807
Fig 1. Logic symbol
11
C1
1 EN1
2 1D
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
mna808
Fig 2. IEC logic symbol
74LVC573A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 19 February 2013
© NXP B.V. 2013. All rights reserved.
2 of 20









No Preview Available !

74LVC573A Даташит, Описание, Даташиты
NXP Semiconductors
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
2 D0
3 D1
4 D2
5 D3
6 D4
7 D5
8 D6
9 D7
11 LE
1 OE
Fig 3. Functional diagram
LATCH
1 to 8
Q0 19
Q1 18
Q2 17
3-STATE Q3 16
OUTPUTS Q4 15
Q5 14
Q6 13
Q7 12
mna809
D0 D1 D2 D3 D4 D5 D6 D7
DQ
LATCH
1
LE LE
DQ
LATCH
2
LE LE
DQ
LATCH
3
LE LE
DQ
LATCH
4
LE LE
DQ
LATCH
5
LE LE
DQ
LATCH
6
LE LE
DQ
LATCH
7
LE LE
DQ
LATCH
8
LE LE
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
mna810
Fig 4. Logic diagram
74LVC573A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 19 February 2013
© NXP B.V. 2013. All rights reserved.
3 of 20










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