74LVC821AD PDF даташит
Спецификация 74LVC821AD изготовлена «NXP Semiconductors» и имеет функцию, называемую «10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State». |
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Детали детали
Номер произв | 74LVC821AD |
Описание | 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State |
Производители | NXP Semiconductors |
логотип |
12 Pages
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INTEGRATED CIRCUITS
74LVC821A
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger
(3-State)
Product specification
1998 Sep 25
Philips
Semiconductors
No Preview Available ! |
Philips Semiconductors
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
Product specification
74LVC821A
FEATURES
• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Supply voltage range of 2.7V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5V
• CMOS low power consumption
• Direct interface with TTL levels
• 10-bit positive edge-triggered register
• Independent register and 3-State buffer operation
• Flow-through pin-out architecture
DESCRIPTION
The 74LVC821A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-state
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type
inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops. The ten flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the contents
of the ten flip-flops is available at the outputs.
When OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
Propagation delay
CP to Qn
Maximum clock frequency
CL = 50 pF;
VCC = 3.3 V
CI Input capacitance
CPD
Power dissipation capacitance per
flip-flop
Notes 1 and 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
TYPICAL
5.4
150
5.0
26
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
ORDERING CODE
74LVC821A D
74LVC821A DB
74LVC821A PW
UNIT
ns
MHz
pF
pF
PKG. DWG. #
SOT137-1
SOT340-1
SOT355-1
1998 Sep 25
2 853-1970 20088
No Preview Available ! |
Philips Semiconductors
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
Product specification
74LVC821A
PIN DESCRIPTION
PIN NUMBER SYMBOL
1 OE
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
23, 22, 21, 20,
19, 18, 17, 16,
15, 14
12
D0 to D9
Q0 to Q9
GND
13 CP
24 VCC
NAME AND FUNCTION
Output enable input
(active LOW)
Data inputs
3-State flip-flop outputs
Ground (0 V)
Clock input (LOW-to-HIGH,
edge-triggered)
Positive supply voltage
FUNCTION TABLE
OPERATING MODES
OE
Load and read register
L
L
Load register and disable outputs
H
H
Hold
L
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH
CP transition
Z = high impedance OFF-state
↑ = LOW–to–HIGH clock transition
NC= no change
INPUTS
CP
↑
↑
↑
↑
H or L
Dn
l
h
l
h
X
INTERNAL FLIP-FLOPS
L
H
L
H
NC
PIN CONFIGURATION
LOGIC SYMBOL
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
SA00413
13
CP
2 D0
Q 0 23
3 D1
Q 1 22
4 D2
Q 2 21
5 D3
Q 3 20
6 D4
Q 4 19
7 D5
Q 5 18
8 D6
Q 6 17
9 D7
Q 7 16
10 D 8
Q 8 15
11 D 9
Q 9 14
OE
1
SA00414
OUTPUTS
Q0 to Q9
L
H
Z
Z
NC
1998 Sep 25
3
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Номер в каталоге | Описание | Производители |
74LVC821A | 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State | NXP Semiconductors |
74LVC821AD | 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State | NXP Semiconductors |
74LVC821ADB | 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State | NXP Semiconductors |
74LVC821APW | 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State | NXP Semiconductors |
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