74LVCH162374ADGG PDF даташит
Спецификация 74LVCH162374ADGG изготовлена «NXP Semiconductors» и имеет функцию, называемую «16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/output tolerant; 3-state». |
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Детали детали
Номер произв | 74LVCH162374ADGG |
Описание | 16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/output tolerant; 3-state |
Производители | NXP Semiconductors |
логотип |
16 Pages
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INTEGRATED CIRCUITS
DATA SHEET
74LVC162374A; 74LVCH162374A
16-bit edge triggered D-type
flip-flop with 30 Ω series termination
resistors; 5 V input/output tolerant;
3-state
Product specification
File under Integrated Circuits, IC24
1999 Aug 05
No Preview Available ! |
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series 74LVC162374A;
termination resistors; 5 V input/output tolerant; 3-state 74LVCH162374A
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• 5 V tolerant input/output for
interfacing with 5 V logic
• Wide supply voltage range of
1.2 to 3.6 V
• Complies with JEDEC standard
no. 8-1A
• CMOS low power consumption
• MULTIBYTE™ flow-through
standard pin-out architecture
• Low inductance multiple power and
ground pins for minimum noise and
ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold
(74LVCH162374A only)
• High impedance when VCC = 0
• Power off disables outputs,
permitting live insertion.
DESCRIPTION
The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate
D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
The 74LVC162374A consists of 2 sections of eight edge-triggered flip-flops.
A clock (CP) input and an output enable (OE) are provided for each octal.
Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.
The flip-flops will store the state of their individual D-inputs that meet the set-up
and hold time requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
The 74LVCH162374A bus hold data inputs eliminates the need for external pull
up resistors to hold unused inputs.
The 74LVC(H)162374A is designed with 30 Ω series termination resistors in
both HIGH and LOW output stages to reduce line noise.
FUNCTION TABLE
See note 1.
OPERATION MODES
Load and read register
Latch register and disable outputs
nOE
L
L
H
H
INPUTS
nCP
↑
↑
↑
↑
nDn
l
h
l
h
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.
INTERNAL
FLIP-FLOPS
L
H
L
H
OUTPUTS
Q0 to Q7
L
H
Z
Z
1999 Aug 05
2
No Preview Available ! |
Philips Semiconductors
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
Product specification
74LVC162374A;
74LVCH162374A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH
fmax
CI
CPD
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per
flip-flop
CONDITIONS
CL = 50 pF; VCC = 3.3 V
VCC = 3.3 V; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
TYPICAL
3.8
150
5.0
30
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
74LVC162374ADL
74LVC162374ADGG
74LVCH162374ADL
74LVCH162374ADGG
VC162374A DL
VC162374A DGG
VCH162374A DL
VCH162374A DGG
TEMPERATURE
RANGE
−40 to +85 °C
PACKAGE
PINS PACKAGE
48 SSOP
48 TSSOP
48 SSOP
48 TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT370-1
SOT362-1
SOT370-1
SOT362-1
PINNING
PIN SYMBOL
1 1OE
2, 3, 5, 6, 8, 9, 11, 12
1Q0 to 1Q7
4, 10, 15, 21, 28, 34, 39, 45 GND
7, 18, 31, 42
VCC
13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7
24 2OE
25 2CP
36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7
47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7
48 1CP
DESCRIPTION
output enable input (active LOW)
3-state flip-flop outputs
ground (0 V)
DC supply voltage
3-state flip-flop outputs
output enable input (active LOW)
clock input
data inputs
data inputs
clock input
1999 Aug 05
3
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74LVCH162374ADGG | 16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/output tolerant; 3-state | NXP Semiconductors |
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