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74LVCH16373ADGG PDF даташит

Спецификация 74LVCH16373ADGG изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State».

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Номер произв 74LVCH16373ADGG
Описание 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVCH16373ADGG Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LVC16373A/74LVCH16373A
16-bit D-type transparent latch with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
Supersedes data of 1997 Aug 22
IC24 Data Handbook
1998 Mar 17
Philips
Semiconductors









No Preview Available !

74LVCH16373ADGG Даташит, Описание, Даташиты
Philips Semiconductors
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
Product specification
74LVC16373A/
74LVCH16373A
FEATURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH167373A only)
High impedance when VCC = 0
PIN CONFIGURATION
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
GND 10
48 1LE
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 VCC
41 1D4
40 1D5
39 GND
DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. One latch enable (LE) input and one output
enable (OE) are provided for each octal. Inputs can be driven from
either 3.3V or 5V devices. In 3-State operation, outputs can handle
5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
The 74LVC(H)16373A consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The 74LVCH16373A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
VCC 18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 VCC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2LE
SW00066
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
Dn to Qn
LE to Qn
CL = 50pF
VCC = 3.3V
CI Input capacitance
CPD
Power dissipation capacitance per latch
VCC = 3.3V
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
48-Pin Plastic SSOP Type III
–40°C to +85°C
74LVC16373A DL
48-Pin Plastic TSSOP Type II
–40°C to +85°C
74LVC16373A DGG
48-Pin Plastic SSOP Type III
–40°C to +85°C
74LVCH16373A DL
48-Pin Plastic TSSOP Type II
–40°C to +85°C
74LVCH16373A DGG
TYPICAL
3.0
3.4
5.0
26
UNIT
ns
pF
pF
NORTH AMERICA
VC16373A DL
VC16373A DGG
VCH16373A DL
VCH16373A DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
1998 Mar 17
2 853-2027 19112









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74LVCH16373ADGG Даташит, Описание, Даташиты
Philips Semiconductors
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
Product specification
74LVC16373A/
74LVCH16373A
PIN DESCRIPTION
PIN NUMBER SYMBOL
1 1OE
2, 3, 5, 6, 8, 9,
11, 12
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17,
19, 20, 22, 23
1Q0 to 1Q7
GND
VCC
2Q0 to 2Q7
24 2OE
25
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
48
2LE
2D0 to 2D7
1D0 to 1D7
1LE
NAME AND FUNCTION
Output enable input
(active LOW)
Data inputs/outputs
Ground (0V)
Positive supply voltage
Data inputs/outputs
Output enable input
(active LOW)
Latch enable input (active
HIGH)
Data inputs
Data inputs
Latch enable input (active
HIGH)
LOGIC SYMBOL
1 24
1OE 2OE
47 1D0
1Q0
46 1D1
44 1D2
1Q1
1Q2
43 1D3
41 1D4
1Q3
1Q4
40 1D5
38 1D6
1Q5
1Q6
37 1D7
1Q7
36 2D0
2Q0
35 2D1
2Q1
33 2D2
2Q2
32 2D3
2Q3
30 2D4
2Q4
29 2D5
2Q5
27 2D6
2Q6
26 2D7
2Q7
1LE 2LE
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
LOGIC DIAGRAM
1D0
1LE
1OE
DQ
LATCH
1
LE LE
1Q0 2D0
2LE
2OE
48 25
SW00067
DQ
LATCH
9
LE LE
2Q0
TO 7 OTHER CHANNELS
FUNCTION TABLE (per section of eight bits)
OPERATING MODES
INPUTS
OE LE
enable and read register
(transparent mode)
LH
LH
latch and read register
LL
LL
latch register and disable outputs
HL
HL
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
TO 7 OTHER CHANNELS
SW00068
INTERNAL
OUTPUTS
Dn
LATCHES
Q0 to Q7
LL
HH
L
H
lLL
hH H
lL
hH
Z
Z
1998 Mar 17
3










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