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74LVQ573 PDF даташит

Спецификация 74LVQ573 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage Octal Latch with 3-STATE Outputs».

Детали детали

Номер произв 74LVQ573
Описание Low Voltage Octal Latch with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LVQ573 Даташит, Описание, Даташиты
May 1998
74LVQ573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVQ573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output Enable
(OE) inputs. The LVQ573 is functionally identical to the
LVQ373 but with inputs and outputs on opposite sides of the
package.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ573SC
74LVQ573SJ
74LVQ573QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011361-1
IEEE/IEC
DS011361-2
DS011361-3
Pin Descriptions
Pin Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
© 1998 Fairchild Semiconductor Corporation DS011361
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74LVQ573 Даташит, Описание, Даташиты
Truth Table
Inputs
Outputs
OE LE D
L HH
On
H
L HL
L
L LX
H XX
O0
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Functional Description
The LVQ573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D-type input changes. When LE is LOW the
latches store the information that was present on the D-type
inputs a setup time preceding the HIGH-to-LOW transition of
LE. The 3-STATE buffers are controlled by the Output En-
able (OE) input. When OE is LOW, the buffers are enabled.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
DS011361-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVQ573 Даташит, Описание, Даташиты
Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground
Current (ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
±50 mA
±400 mA
−65˚C to +150˚C
±300 mA
DC Electrical Characteristics
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
2.0V to 3.6V
0V to VCC
0V to VCC
−40˚C to +85˚C
VIN from 0.8V to 2.0V
VCC @ 3.0V
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for ac-
tual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
VOL Maximum Low Level
Output Voltage
IIN
IOLD
IOHD
ICC
IOZ
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
3-STATE
Leakage Curent
VOLP
VOLV
VIHD
VILD
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
VCC
(V)
TA = +25˚C
TA = −40˚C to +85˚C Units
Conditions
Typ Guaranteed Limits
3.0 1.5
2.0
3.0 1.5
0.8
3.0 2.99
3.0
2.9
2.58
3.0 0.002
3.0
0.1
0.36
3.6 ±0.1
2.0
0.8
2.9
2.48
0.1
0.44
±1.0
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
V VIN = VIL or VIH (Note 3)
IOH = −12 mA
V IOUT = 50 µA
V VIN = VIL or VIH (Note 3)
IOL = 12 mA
µA VI = VCC, GND
3.6 36 mA VOLD = 0.8 VMax (Note 5)
3.6 −25 mA VOHD = 2.0V VMin (Note 5)
3.6 4.0 40.0 µA VIN = VCC or GND
3.6 ±0.25
3.3 0.4
0.8
±2.5
VI (OE) = VIL, VIH
µA VI = VCC, GND
VO = VCC, GND
V (Notes 6, 7)
3.3 −0.4 −0.8
V (Notes 6, 7)
3.3 1.6
2.0
V (Notes 6, 8)
3.3 1.6
0.8
V (Notes 6, 8)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75for commercial temperature range is guaranteed for.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
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