74LVT322245 Datasheet PDF - Fairchild Semiconductor
| Part Number | 74LVT322245 | |
| Description | Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs | |
| Manufacturers | Fairchild Semiconductor | |
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May 2002
Revised May 2002
74LVT322245 • 74LVTH322245
Low Voltage 32-Bit Transceiver with 3-STATE Outputs
and 25Ω Series Resistors in A Port Outputs
General Description
The LVT322245 and LVTH322245 contain thirty-two non-
inverting bidirectional buffers with 3-STATE outputs and are
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 32-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVT322245 and LVTH322245 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH322245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The
LVT322245 and LVTH322245 are fabricated with an
advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322245)
s Also available without bushold feature (74LVT322245)
s Live insertion/extraction permitted
s Power Up/Power Down high impedance provides
glitch-free bus loading
s A Port outputs include equivalent series resistance of
25Ω making external termination resistors unnecessary
and reducing overshoot and undershoot
s A Port outputs source/sink ±12 mA
B Port outputs source/sink −32 mA/+64 mA
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number Package Number
Package Description
74LVT322245G
(Note 1) (Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVTH322245G
(Note 1) (Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code “G” indicates TRAYS.
Note 2: Devices also available in TAPE and REEL. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500408
www.fairchildsemi.com
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DC Electrical Characteristics (Continued)
Symbol
Parameter
VCC TA = −40°C to +85°C Units
(V) Min Max
Conditions
IPU/PD
IOZL
IOZL
(Note 5)
Power Up/Down
3-STATE Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
0–1.5V
3.6
3.6
±100
−5
−5
µA VO = 0.5V to 3.0V
VI = GND to VCC
µA VO = 0.5V
µA VO = 0.0V
IOZH
IOZH
(Note 5)
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6 5 µA VO = 3.0V
3.6 5 µA VO = 3.6V
IOZH+
ICCH
ICCL
ICCZ
ICCZ+
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
VCC1 or VCC2
VCC1 or VCC2
VCC1 or VCC2
VCC1 or VCC2
3.6
3.6
3.6
3.6
3.6
10
0.19
5
0.19
0.19
µA VCC < VO ≤ 5.5V
mA Outputs HIGH
mA Outputs LOW
mA Outputs Disabled
mA VCC ≤ VO ≤ 5.5V,
Outputs Disabled
∆ICC
Increase in Power Supply Current
(Note 8)
VCC1 or VCC2
Note 5: Applies to bushold versions only (74LVTH322245).
3.6
0.2 mA One Input at VCC − 0.6V
Other Inputs at VCC or GND
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 9)
Symbol
Parameter
VCC TA = 25°C
Units
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
V
V
Conditions
CL = 50 pF RL = 500Ω
(Note 10)
(Note 10)
AC Electrical Characteristics
Symbol
Parameter
tPLH Propagation Delay Data to A Port Output
tPHL
tPLH Propagation Delay Data to B Port Output
tPHL
tPZH Output Enable Time for A Port Output
tPZL
tPZH Output Enable Time for B Port Output
tPZL
tPHZ Output Disable Time for A Port Output
tPLZ
tPHZ Output Disable Time for B Port Output
tPLZ
TA = −40°C to +85°C
CL = 50 pF, RL = 500Ω
VCC = 3.3V ± 0.3V
VCC = 2.7V
Min Max Min Max
1.0 4.0 1.0 4.6
1.0 3.7 1.0 4.1
1.0 3.5 1.0 3.9
1.0 3.5 1.0 3.9
1.0 5.3 1.0 6.3
1.0 5.6 1.0 7.2
1.0 4.6 1.0 5.4
1.0 5.3 1.0 6.9
1.5 5.6 1.5 6.3
1.5 5.5 1.5 5.5
1.5 5.4 1.5 6.1
1.5 5.1 1.5 5.4
Capacitance (Note 11)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
CI/O
Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
ns
ns
ns
ns
ns
ns
Units
pF
pF
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| Information | Total 6 Pages | |
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