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74LVT32374G PDF даташит

Спецификация 74LVT32374G изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs».

Детали детали

Номер произв 74LVT32374G
Описание Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LVT32374G Даташит, Описание, Даташиты
April 2001
Revised June 2002
74LVT32374 74LVTH32374
Low Voltage 32-Bit D-Type Flip-Flop
with 3-STATE Outputs
General Description
The LVT32374 and LVTH32374 contain thirty-two non-
inverting D-type flip-flops with 3-STATE outputs and are
intended for bus oriented applications. The device is byte
controlled. A buffered clock (CP) and Output Enable (OE)
are common to each byte and can be shorted together for
full 32-bit operation.
The LVTH32374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT32374 and LVTH32374
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32374)
s Also available without bushold feature (74LVT32374)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number
Package
Number
Package Description
74LVT32374G
(Note 1)(Note 2)
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVTH32374G
(Note 1)(Note 2)
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500452
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74LVT32374G Даташит, Описание, Даташиты
Connection Diagram
Pin Descriptions
Pin Names
OEn
CPn
I0I31
O0O31
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
FBGA Pin Assignments
(Top Thru View)
123456
A
O1
O0 OE1 CP1
I0
I1
B O3 O2 GND GND I2
I3
C
O5
O4 VCC1 VCC1
I4
I5
D O7 O6 GND GND I6
I7
E O9 O8 GND GND I8
I9
F O11 O10 VCC1 VCC1 I10 I11
G O13 O12 GND GND I12 I13
H
O14 O15 OE2 CP2
I15
I14
J
O17 O16 OE3 CP3
I16
I17
K O19 O18 GND GND I18 I19
L O21 O20 VCC2 VCC2 I20 I21
M O23 O22 GND GND I22 I23
N O25 O24 GND GND I24 I25
P O27 O26 VCC2 VCC2 I26 I27
R O29 O28 GND GND I28 I29
T
O30 O31 OE4 CP4
I31
I30
Functional Description
The LVT32374 and LVTH32374 consist of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins
can be shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common
to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their
individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With
the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go
to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Truth Tables
Inputs
CP1
OE1
L
L
LL
XH
I0I7
H
L
X
X
Outputs
O0O7
H
L
Oo
Z
Inputs
CP2
OE2
I8I15
L H
L L
LLX
XHX
Outputs
O8O15
H
L
Oo
Z
Inputs
CP3
OE3
L
L
LL
XH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
I16I23
H
L
X
X
Outputs
O16O23
H
L
Oo
Z
Inputs
CP4
OE4
L
L
I24I31
H
L
LLX
XHX
Z = HIGH Impedance
Oo = Previous Oo before HIGH-to-LOW of CP
Outputs
O24O31
H
L
Oo
Z
www.fairchildsemi.com
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74LVT32374G Даташит, Описание, Даташиты
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
VCC1 is associated with Bytes 1 and 2.
VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
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Номер в каталогеОписаниеПроизводители
74LVT32374Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE OutputsFairchild Semiconductor
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