DataSheet26.com

74LVT373WM PDF даташит

Спецификация 74LVT373WM изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage Octal Transparent Latch with 3-STATE Outputs».

Детали детали

Номер произв 74LVT373WM
Описание Low Voltage Octal Transparent Latch with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

7 Pages
scroll

No Preview Available !

74LVT373WM Даташит, Описание, Даташиты
September 1999
Revised October 1999
74LVT373 • 74LVTH373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfying
the input timing requirements is latched. Data appears on
the bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in a high impedance state.
The LVTH373 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT373 and LVTH373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH373), also
available without bushold feature (74LVT373).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 373
Ordering Code:
Order Number
74LVT373WM
74LVT373SJ
74LVT373MTC
74LVTH373WM
74LVTH373SJ
74LVTH373MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012015
www.fairchildsemi.com









No Preview Available !

74LVT373WM Даташит, Описание, Даташиты
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Truth Table
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Functional Description
The LVT373 and LVTH373 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input
changes. When LE is LOW, the latches store the informa-
tion that was present on the D inputs a setup time preced-
Logic Diagram
Inputs
Outputs
LE OE Dn On
XHXZ
HL L L
H L HH
L L X O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
ing the HIGH-to-LOW transition of LE. The 3-STATE
standard outputs are controlled by the Output Enable (OE)
input. When OE is LOW, the standard outputs are in the 2-
state mode. When OE is HIGH, the standard outputs are in
the high impedance mode but this does not interfere with
entering new data into the latches.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2









No Preview Available !

74LVT373WM Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
0.5 to +4.6
0.5 to +7.0
0.5 to +7.0
0.5 to +7.0
50
50
64
128
±64
±128
65 to +150
Recommended Operating Conditions
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 2)
VI < GND
VO < GND
VO > VCC Output at HIGH State
VO > VCC Output at LOW State
Units
V
V
V
V
mA
mA
mA
mA
mA
°C
Symbol
Parameter
Min
Max
Units
VCC Supply Voltage
2.7 3.6 V
VI Input Voltage
0 5.5 V
IOH HIGH Level Output Current
32 mA
IOL LOW Level Output Current
64 mA
TA Free-Air Operating Temperature
40 85 °C
t/V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0 10 ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: IO Absolute Maximum Rating must be observed.
3 www.fairchildsemi.com










Скачать PDF:

[ 74LVT373WM.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
74LVT373WMLow Voltage Octal Transparent Latch with 3-STATE OutputsFairchild Semiconductor
Fairchild Semiconductor

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск