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PDF 74LVT374 Data sheet ( Hoja de datos )
| Número de pieza | 74LVT374 | |
| Descripción | Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 1999
Revised October 1999
74LVT374 • 74LVTH374
Low Voltage Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The LVT374 and LVTH374 are high-speed, low-power
octal D-type flip-flops featuring separate D-type inputs for
each flip-flop and 3-STATE outputs for bus-oriented appli-
cations. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The LVTH374 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT374 and LVTH374
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bus-Hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH374),
also available without bushold feature (74LVT374).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 374
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVT374WM
74LVT374SJ
74LVT374MTC
74LVTH374WM
74LVTH374SJ
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012016
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fMAX
Maximum Clock Frequency
tPHL Propagation Delay
tPLH
CP to On
tPZL Output Enable Time
tPZH
tPLZ Output Disable Time
tPHZ
tW Pulse Width
tS Setup Time
tH Hold Time
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
Capacitance (Note 11)
TA = −40°C to +85°C
CL = 50 pF, RL = 500Ω
VCC = 3.3V ± 0.3V
VCC = 2.7V
Min
Typ
(Note 10)
Max
Min
Max
160 160
1.8 4.9 1.8 5.1
1.8 4.8 1.8 5.2
1.3 5.0 1.3 5.8
1.6 4.7 1.6 5.3
1.9 4.6 1.9 4.9
2.0 4.7 2.0 5.0
3.0 3.0
1.5 2.0
0.8 0.0
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
3
5
Units
MHz
ns
ns
ns
ns
ns
ns
Units
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74LVT374.PDF ] | |
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