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74LVT74PWDH PDF даташит

Спецификация 74LVT74PWDH изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «3.3V Dual D-type flip-flop».

Детали детали

Номер произв 74LVT74PWDH
Описание 3.3V Dual D-type flip-flop
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVT74PWDH Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LVT74
3.3V Dual D-type flip-flop
Product specification
IC24 Data Handbook
Philips
Semiconductors
1996 Aug 28









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74LVT74PWDH Даташит, Описание, Даташиты
Philips Semiconductors
3.3V Dual D-type flip-flop
Product specification
74LVT74
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
Tamb = 25°C;
GND = 0V
tPLH
tPHL
Propagation
delay
CPn to Qn
CL = 50pF;
VCC = 3.3V
CIN
Input
capacitance
VI = 0V or 3.0V
ICC
Total supply
current
VCC = 3.6V
TYPICAL UNIT
3.1
3.6
ns
3 pF
0.5 mA
PIN CONFIGURATION
RD0 1
D0 2
CP0 3
SD0 4
Q0 5
Q0 6
GND 7
14 VCC
13 RD1
12 D1
11 CP1
10 SD1
9 Q1
8 Q1
LOGIC SYMBOL
2 12
SF00045
3
4
1
11
10
13
VCC = Pin 14
GND = Pin 7
D0 D1
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
56 98
SA00359
DESCRIPTION
The 74LVT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
PIN DESCRIPTION
PIN NUMBER SYMBOL
NAME AND FUNCTION
2, 12
D0, D1 Data inputs
3, 11
CP0, CP1 Clock inputs (active rising edge)
4, 10
SD0, SD1 Set inputs (active LOW)
1, 13
RD0, RD1 Reset inputs (active LOW)
5, 6, 8, 9
Qn, Qn Data outputs
LOGIC SYMBOL (IEEE/IEC)
4&
S
3
C1
2
1D
1
R
10
S
11
C2
12 2D
13 R
5
6
9
8
SF00047
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP
14-Pin Plastic TSSOP
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT74 D
74LVT74 DB
74LVT74 PW
NORTH AMERICA
74LVT74 D
74LVT74 DB
74LVT74PW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
1996 Aug 28
2 853-1872 17244









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74LVT74PWDH Даташит, Описание, Даташиты
Philips Semiconductors
3.3V Dual D-type flip-flop
Product specification
74LVT74
LOGIC DIAGRAM
FUNCTION TABLE
SD 4, 10
INPUTS
OUTPUTS
SD RD CP D Q Q
OPERATING
MODE
L H X X H L Asynchronous set
RD 1, 13
5, 9
Q
H L X X L H Asynchronous reset
L L X X H H Undetermined*
CP 3, 11
D 2, 12
VCC = Pin 14
GND = Pin 7
ABSOLUTE MAXIMUM RATINGS1, 2
6, 8
Q
SF00048
H H h H L Load “1”
H H l L H Load “0”
H H X NC NC Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high
clock transition
NC= No change from the previous setup
X = Don’t care
= Low-to-high clock transition
= Not low-to-high clock transition
* = This setup is unstable and will change when either set
or reset return to the high level.
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
VCC DC supply voltage
IIK DC input diode current
VI DC input voltage3
VI < 0
–0.5 to +4.6
–50
–0.5 to +7.0
V
mA
V
IOK
VOUT
IOUT
DC output diode current
DC output voltage3
DC output current
VO < 0
Output in Off or High state
Output in High state
Output in Low state
–50
–0.5 to +7.0
–32
64
mA
V
mA
Tstg Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VIH
VIL
IOH
IOL
t/v
Tamb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
LIMITS
MIN MAX
2.7 3.6
0 5.5
2.0
0.8
–20
32
10
–40 +85
UNIT
V
V
V
V
mA
mA
ns/V
°C
1996 Aug 28
3










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