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74LVTH16374MTD PDF даташит

Спецификация 74LVTH16374MTD изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs».

Детали детали

Номер произв 74LVTH16374MTD
Описание Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LVTH16374MTD Даташит, Описание, Даташиты
January 1999
Revised April 1999
74LVT16374 • 74LVTH16374
Low Voltage 16-Bit D-Type Flip-Flop with
3-STATE Outputs
General Description
The LVT16374 and LVTH16374 contain sixteen non-invert-
ing D-type flip-flops with 3-STATE outputs and is intended
for bus oriented applications. The device is byte controlled.
A buffered clock (CP) and Output Enable (OE) are com-
mon to each byte and can be shorted together for full 16-bit
operation.
The LVTH16374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT16374 and LVTH16374
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V
VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16374), also
available without bushold feature (74LVT16374).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16374MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16374MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16374MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16374MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS012022.prf
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74LVTH16374MTD Даташит, Описание, Даташиты
Connection Diagram
Pin Descriptions
Pin Names
OEn
CPn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
Truth Tables
Inputs
CP1
OE1
L
L
I0–I7
H
L
LL
X
XH
X
Outputs
O0–O7
H
L
Oo
Z
Inputs
CP2
OE2
L
L
I8–I15
H
L
LL
X
XH
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
Oo = Previous Oo before HIGH to LOW of CP
Outputs
O8–O15
H
L
Oo
Z
Functional Description
The LVT16374 and LVTH16374 consist of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common
to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their
individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With
the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go
to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
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74LVTH16374MTD Даташит, Описание, Даташиты
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that these diagrams are provided for the understanding of logic operaiton and should not be used to estimate propagation delays.
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Номер в каталогеОписаниеПроизводители
74LVTH16374MTDLow Voltage 16-Bit D-Type Flip-Flop with 3-STATE OutputsFairchild Semiconductor
Fairchild Semiconductor

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