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74LVTH16835MTD PDF даташит

Спецификация 74LVTH16835MTD изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary)».

Детали детали

Номер произв 74LVTH16835MTD
Описание Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary)
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LVTH16835MTD Даташит, Описание, Даташиты
Preliminary
May 2000
Revised May 2000
74LVTH16835
Low Voltage 18-Bit Universal Bus Driver
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16835 consists of 18-bit universal bus drivers
which combine D-type latches and D-type flip-flops to allow
data flow in transparent, latched, or clocked modes. Data
flow from A to Y is controlled by the output-enable (OE)
input. This device operates in the transparent mode when
the latch-enable (LE) input is HIGH. The A data is latched if
the clock (CLK) input is held at a HIGH or LOW logic level.
If LE is LOW, the A-bus data is stored in the latch/flip-flop
on the LOW-to-HIGH transition of the CLK. When OE is
HIGH, the outputs are in the high-impedance state.
The LVTH16835 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The bus driver is designed for low voltage (3.3V) VCC appli-
cations, but with the capability to provide a TTL interface to
a 5V environment. The LVTH16835 is fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH16835MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS500102
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74LVTH16835MTD Даташит, Описание, Даташиты
Connection Diagram
Preliminary
Pin Descriptions
Pin Names
Description
A1A18
Y1Y18
CLK
Data Register Inputs
3-STATE Outputs
Clock Pulse Input
OE Output Enable Input
LE Latch Enable Input
Truth Table
Inputs
OE LE CLK A
Output
Y
HXXX
Z
L HX L
L
LHXH
H
LLL
L
L L H
H
L L H X Y0 (Note 1)
L L L X Y0 (Note 2)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
↑ = HIGH-to-LOW Clock Transition
Note 1: Output level before the indicated steady-state input conditions
were established, provided that CLK was HIGH before LE went LOW.
Note 2: Output level before the indicated steady-state input conditions
were established.
Logic Diagram
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74LVTH16835MTD Даташит, Описание, Даташиты
Preliminary
Absolute Maximum Ratings(Note 3)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
0.5 to +4.6
0.5 to +7.0
0.5 to +7.0
0.5 to +7.0
50
50
64
128
±64
±128
65 to +150
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
VI < GND
VO < GND
VO > VCC Output at HIGH State
VO > VCC Output at LOW State
Units
V
V
V
V
mA
mA
mA
mA
mA
°C
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
VCC Supply Voltage
2.7 3.6
V
VI Input Voltage
0 5.5 V
IOH HIGH-Level Output Current
32 mA
IOL LOW-Level Output Current
64 mA
TA Free-Air Operating Temperature
40 85
°C
t/V
Input Edge Rate, VIN = 0.8V2.0V, VCC = 3.0V
0 10 ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: IO Absolute Maximum Rating must be observed.
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