74LVTH273MTC PDF даташит
Спецификация 74LVTH273MTC изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage Octal D-Type Flip-Flop with Clear». |
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Детали детали
Номер произв | 74LVTH273MTC |
Описание | Low Voltage Octal D-Type Flip-Flop with Clear |
Производители | Fairchild Semiconductor |
логотип |
6 Pages
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July 1999
Revised July 1999
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
General Description
The LVTH273 is a high-speed, low-power positive-edge-
triggered octal D-type flip-flop featuring separate D-type
inputs for each flip-flop. A buffered Clock (CP) and Clear
(CLR) are common to all flip-flops.
The state of each D-type input, one setup time before the
positive clock transition, is transferred to the corresponding
flip-flop’s output.
The LVTH273 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH273 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold on the data inputs eliminate the need for
external pull-up resistors to hold unused inputs
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 273
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVTH273WM
74LVTH273SJ
74LVTH273MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS500100
www.fairchildsemi.com
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Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
CLR
O0–O7
Truth Table
Description
Data Inputs
Clock Pulse Input
Clear
Outputs
Inputs
Dn CP CLR
H H
L H
X H or L H
XXL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Oo = Previous Oo before HIGH-to-LOW of CP
Outputs
On
H
L
Oo
L
Functional Description
The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear
are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input sig-
nal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1)
Symbol
Parameter
VCC Supply Voltage
VI DC Input Voltage
VO DC Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−50
−50
64
128
±64
±128
−65 to +150
Recommended Operating Conditions
Conditions
Output in HIGH or LOW State (Note 2)
VI < GND
VO < GND
VO > VCC Output at HIGH State
VO > VCC Output at LOW State
Units
V
V
V
mA
mA
mA
mA
mA
°C
Symbol
Parameter
Min Max Units
VCC Supply Voltage
2.7 3.6
V
VI Input Voltage
0 5.5
V
IOH HIGH Level Output Current
−32 mA
IOL LOW Level Output Current
64 mA
TA Free-Air Operating Temperature
−40 85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0 10 ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
VIK Input Clamp Diode Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
II(HOLD) Bushold Input Minimum Drive
II(OD)
II
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
IOFF
ICCH
ICCL
∆ICC
Power Off Leakage Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
(Note 6)
VCC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
0
3.6
3.6
3.6
TA =−40°C to +85°C
Min Typ
Max
(Note 3)
−1.2
2.0
0.8
VCC − 0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
−75
500
−500
10
±1
−5
1
±100
0.19
5
0.2
Units
Conditions
V II = −18 mA
V VO ≤ 0.1V or
V VO ≥ VCC − 0.1V
IOH = −100 µA
V IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
V IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
µA VI = 0.8V
VI = 2.0V
(Note 4)
µA
(Note 5)
µA VI = 5.5V
µA VI = 0V or VCC
µA VI = 0V
µA VI = VCC
µA 0V ≤ VI or VO ≤ 5.5V
mA Outputs HIGH
mA Outputs LOW
mA One Input at VCC − 0.6V
Other Inputs at VCC or GND
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