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74LVTH32244GX PDF даташит

Спецификация 74LVTH32244GX изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary)».

Детали детали

Номер произв 74LVTH32244GX
Описание Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary)
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LVTH32244GX Даташит, Описание, Даташиты
Preliminary
January 2001
Revised August 2001
74LVT32244 74LVTH32244
Low Voltage 32-Bit Buffer/Line Driver
with 3-STATE Outputs (Preliminary)
General Description
The LVT32244 and LVTH32244 contain thirty-two non-
inverting buffers with 3-STATE outputs designed to be
employed as a memory and address driver, clock driver, or
bus oriented transmitter/receiver. The device is nibble con-
trolled. Individual 3-STATE control inputs can be shorted
together for 8-bit, 16-bit, or 32-bit operation.
The LVTH32244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT32244 and
LVTH32244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32244),
also available without bushold feature (74LVT32244).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Order Number Package Number
Package Description
74LVT32244GX
(Note 1)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [Tape and Reel]
74LVTH32244GX
(Note 1)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [Tape and Reel]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500434
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74LVTH32244GX Даташит, Описание, Даташиты
Connection Diagram
(Top Thru View)
Pin Descriptions
Pin Names
Description
OEn
I0–I31
O0–O31
Output Enable Input (Active LOW)
Inputs
Outputs
Pin Assignments for FBGA
123456
A O1 O0 OE1 OE2 I0
I1
B O3 O2 GND GND I2
I3
C
O5
O4 VCC1 VCC1
I4
I5
D O7 O6 GND GND I6
I7
E O9 O8 GND GND I8
I9
F O11 O10 VCC1 VCC1 I10 I11
G O13 O12 GND GND I12 I13
H O14 O15 OE4 OE3 I15 I14
J O17 O16 OE5 OE6 I16 I17
K O19 O18 GND GND I18 I19
L O21 O20 VCC2 VCC2 I20 I21
M O23 O22 GND GND I22 I23
N O25 O24 GND GND I24 I25
P O27 O26 VCC2 VCC2 I26 I27
R O29 O28 GND GND I28 I29
T O30 O31 OE8 OE7 I31 I30
Preliminary
Truth Tables
Inputs
OE1
L
L
H
I0-I3
L
H
X
Outputs
O0-O3
L
H
Z
Inputs
OE2
L
L
H
I4-I7
L
H
X
Outputs
O4-O7
L
H
Z
Inputs
OE3
L
L
H
I8-I11
L
H
X
Outputs
O8O11
L
H
Z
Inputs
OE4
L
L
H
I12-I15
L
H
X
Outputs
O12-O15
L
H
Z
Inputs
OE5
L
L
H
I16-I19
L
H
X
Outputs
O16-O19
L
H
Z
Inputs
OE6
L
L
H
I20-I23
L
H
X
Outputs
O20-O23
L
H
Z
Inputs
OE7
L
L
H
I24-I27
L
H
X
Outputs
O24-O27
L
H
Z
Inputs
Outputs
OE8
I28-I31
O28-O31
LL
L
LH
H
HX
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
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74LVTH32244GX Даташит, Описание, Даташиты
Preliminary
Functional Description
The 74LVT32244 and 74LVTH32244 contain thirty-two
non-inverting buffers with 3-STATE outputs. The device is
nibble (4 bits) controlled with each nibble functioning identi-
cally, but independent of the other. The control pins can be
shorted together to obtain full 32-bit operation. The
Logic Diagrams
3-STATE outputs are controlled by an Output Enable (OEn)
input. When OEn is LOW, the outputs are in the 2-state
mode. When OEn is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the inputs.
Byte 1
Byte 2
Byte 3
Byte 4
VCC1 is associated with Bytes 1 and 2.
VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Fairchild Semiconductor

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