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74LVTH543MTC PDF даташит

Спецификация 74LVTH543MTC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage Octal Registered Transceiver with 3-STATE Outputs».

Детали детали

Номер произв 74LVTH543MTC
Описание Low Voltage Octal Registered Transceiver with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LVTH543MTC Даташит, Описание, Даташиты
April 2000
Revised April 2000
74LVTH543
Low Voltage Octal Registered Transceiver
with 3-STATE Outputs
General Description
The LVTH543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow.
The LVTH543 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
This octal registered transceiver is designed for low-volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVTH543 is
fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 543
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH543WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH543MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CEAB, CEBA
A0–A7
B0–B7
Description
Output Enable Inputs
Latch Enable Inputs
Chip Enable Inputs
Side A Inputs or
3-STATE Outputs
Side B Inputs or
3-STATE Outputs
© 2000 Fairchild Semiconductor Corporation DS012448
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74LVTH543MTC Даташит, Описание, Даташиты
Logic Symbols
IEEE/IEC
Logic Diagram
Functional Description
The LVTH543 contains two sets of D-type latches, with
separate input and output controls for each. For data flow
from A to B, for example, the A to B Enable (CEAB) input
must be LOW in order to enter data from the A Port or take
data from the B Port as indicated in the Data I/O Control
Table. With CEAB LOW, a low signal on (LEAB) input
makes the A to B latches transparent; a subsequent LOW-
to-HIGH transition of the LEAB line puts the A latches in
the storage mode and their outputs no longer change with
the A inputs. With CEAB and OEAB both LOW, the B out-
put buffers are active and reflect the data present on the
output of the A latches. Control of data flow from B to A is
similar, but using the CEBA, LEBA and OEBA.
Data I/O Control Table
Inputs
Latch Status
CEAB LEAB OEAB
Output
Buffers
HXX
Latched
High Z
XHX
Latched
L
L
X Transparent
XXH
— High Z
LXL
— Driving
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note: A-to-B data flow shown; B-to-A flow control is the same, except
using CEBA, LEBA, and OEBA.
Please not that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVTH543MTC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
0.5 to +4.6
0.5 to +7.0
0.5 to +7.0
0.5 to +7.0
50
50
64
128
±64
±128
65 to +150
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 2)
VI < GND
VO < GND
VO > VCC Output at HIGH State
VO > VCC Output at LOW State
Units
V
V
V
V
mA
mA
mA
mA
mA
°C
Recommended Operating Conditions
Symbol
Parameter
Min Max Units
VCC Supply Voltage
2.7 3.6
V
VI Input Voltage
0 5.5
V
IOH HIGH Level Output Current
IOL LOW Level Output Current
32
mA
64
TA Free-Air Operating Temperature
40 85
°C
t/V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0 10 ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: IO Absolute Maximum Rating must be observed.
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Номер в каталогеОписаниеПроизводители
74LVTH543MTCLow Voltage Octal Registered Transceiver with 3-STATE OutputsFairchild Semiconductor
Fairchild Semiconductor

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