DataSheet26.com

74LVTH652MTC PDF даташит

Спецификация 74LVTH652MTC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage Octal Transceiver/Register with 3-STATE Outputs».

Детали детали

Номер произв 74LVTH652MTC
Описание Low Voltage Octal Transceiver/Register with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

8 Pages
scroll

No Preview Available !

74LVTH652MTC Даташит, Описание, Даташиты
April 2000
Revised April 2000
74LVTH652
Low Voltage Octal Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function. (See Functional
Description).
The LVTH652 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
This octal transceiver/register is designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVTH652 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining
low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 652
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH652WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH652MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS012018
www.fairchildsemi.com









No Preview Available !

74LVTH652MTC Даташит, Описание, Даташиты
Pin Descriptions
Pin Names
A0–A7
B0–B7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Inputs
Connection Diagram
Truth Table
(Note 1)
Inputs
OEAB OEBA CPAB CPBA
SAB SBA
Inputs/Outputs
A0 thru A7
B0 thru B7
Operating Mode
L H H or L H or L X X Input
Input
Isolation
 L H
XX
Store A and B Data
X H
H or L X
X Input
Not Specified Store A, Hold B
 H H
X X Input
Output
Store A in Both Registers
L X H or L
X X Not Specified Input
Hold A, Store B
 L L
X X Output
Input
Store B in Both Registers
LL
X
X X L Output
Input
Real-Time B Data to A Bus
LL
X
H or L X
H
Store B Data to A Bus
HH
X
X L X Input
Output
Real-Time A Data to B Bus
H H H or L X
HX
Stored A Data to B Bus
H L H or L H or L
H = HIGH Voltage Level L = LOW Voltage Level
H H Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
X = Immaterial
 = LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2









No Preview Available !

74LVTH652MTC Даташит, Описание, Даташиты
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management functions that can be performed with the
LVTH652.
Data on the A or B data bus, or both can be stored in the
internal D-type flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D-type flip-flops by simulta-
neously enabling OEAB and OEBA. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
OEAB OEBA CPAB CPBA
L LXX
SAB
X
SBA
L
Storage
OEAB OEBA CPAB CPBA
HHXX
Transfer Storage
Data to A or B
SAB
L
SBA
X
OEAB
X
L
L
OEBA
H
X
H
CPAB
X
CPBA
X
SAB
X
X
X
SBA
X
X
X
OEAB OEBA CPAB CPBA
H L H or L H or L
SAB
H
SBA
H
3 www.fairchildsemi.com










Скачать PDF:

[ 74LVTH652MTC.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
74LVTH652MTCLow Voltage Octal Transceiver/Register with 3-STATE OutputsFairchild Semiconductor
Fairchild Semiconductor

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск