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74LVX163M PDF даташит

Спецификация 74LVX163M изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage Synchronous Binary Counter with Synchronous Clear».

Детали детали

Номер произв 74LVX163M
Описание Low Voltage Synchronous Binary Counter with Synchronous Clear
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LVX163M Даташит, Описание, Даташиты
October 1996
Revised March 1999
74LVX163
Low Voltage Synchronous Binary Counter with
Synchronous Clear
General Description
The LVX163 is a synchronous modulo-16 binary counter.
This device is synchronously presettable for application in
programmable dividers and has two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
multistage counters. The CLK input is active on the rising
edge. Both PE and MR inputs are active on low logic lev-
els. Presetting is synchronous to rising edge of the CLK
and the Clear function of the LVX163 is synchronous to the
CLK. Two enable inputs (CEP and CET) and Carry Output
are provided to enable easy cascading of counters, which
facilitates easy implementation of n-bit counters without
using external gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise and dynamic
threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LVX163SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX163MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin
Names
CEP
CET
CP
MR
P0–P3
PE
Q0–Q3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Synchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs
Terminal Count Output
© 1999 Fairchild Semiconductor Corporation DS012157.prf
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74LVX163M Даташит, Описание, Даташиты
Functional Description
The LVX163 counts in modulo-16 binary sequence. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. Thus all changes of the Q outputs occur as a result
of, and synchronous with, the LOW-to-HIGH transition of
the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: synchronous
reset, parallel load, count-up and hold. Four control
inputs—Synchronous Reset (MR), Parallel Enable (PE),
Count Enable Parallel (CEP) and Count Enable Trickle
(CET)—determine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides count-
ing and parallel loading and allows all outputs to go LOW
on the next rising edge of CP. A LOW signal on PE over-
rides counting and allows information on the Parallel Data
(Pn) inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The LVX163 uses D-type edge-triggered flip-flops and
changing the MR, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min in
the Up mode, or min to max in the Down mode, to start its
final cycle. Since this final cycle takes 16 clocks to com-
plete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters. When the Parallel Enable (PE) is LOW, the paral-
lel data outputs O0–O3 are active and follow the flip-flop Q
outputs. A HIGH signal on PE forces O0–O3 to the High
impedance state but does not prevent counting, loading or
resetting.
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table
MR PE CET CEP Action on the Rising
Clock Edge ( )
LX X
X Reset (Clear)
HL
HH
X
H
X Load (Pn Qn)
H Count (Increment)
HH
L
X No Change (Hold)
HH
X
L No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
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74LVX163M Даташит, Описание, Даташиты
State Diagram
Block Diagram
FIGURE 1.
FIGURE 2.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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