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PDF 74VCX162245 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX162245 | |
| Descripción | Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in A Port Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1996
Revised June 2005
74VCX162245
Low Voltage 16-Bit Bidirectional Transceiver
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistors in A Port Outputs
General Description
The VCX162245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. Each
byte has separate 3-STATE control inputs which can be
shorted together for full 16-bit operation. The T/R inputs
determine the direction of data flow through the device.
The OE inputs disable both the A and B ports by placing
them in a high impedance state.
The 74VCX162245 is designed for low voltage (1.4V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX162245 is also designed with 26: series resis-
tance in the A Port outputs. This design reduces line noise
in applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74VCX162245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26: series resistors in A port outputs
s tPD (B to A)
3.4 ns max for 3.0V to 3.6V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL A outputs)
r12 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model ! 2000V
Machine model !200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX162245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin
Names
OEn
T/Rn
A0–A15
B0–B15
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 2005 Fairchild Semiconductor Corporation DS500048
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 6)
Symbol
Parameter
Conditions
VCC TA 40qC to 85qC
Figure
Units
(V) Min Max
Number
tPHL,
tPLH
Propagation Delay
B to A
CL 30 pF, RL 500:
3.3 r 0.3
0.8
3.4
2.5 r 0.2
1.0
4.3
Figures
1, 2
1.8 r 0.15
1.5
8.6
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.0
17.2
Figures
5, 6
tPZL,
tPZH
Output Enable Time
B to A
CL 30 pF, RL 500:
3.3 r 0.3
0.8
4.2
2.5 r 0.2
1.0
5.7
Figures
1, 3, 4
1.8 r 0.15
1.5
9.8
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.0
19.6
Figures
5, 7, 8
tPLZ,
tPHZ
Output Disable Time
B to A
CL 30 pF, RL 500:
3.3 r 0.3
0.8
4.1
2.5 r 0.2
1.0
4.8
Figures
1, 3, 4
1.8 r 0.15
1.5
8.6
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.0
17.2
Figures
5, 7, 8
tPHL,
tPLH
Propagation Delay
A to B
CL 30 pF, RL 500:
3.3 r 0.3
0.8
2.5
2.5 r 0.2
1.0
3.0
Figures
1, 2
1.8 r 0.15
1.5
6.0
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.0
12.0
Figures
5, 6
tPZL,
tPZH
Output Enable Time
A to B
CL 30 pF, RL 500:
3.3 r 0.3
0.8
3.5
2.5 r 0.2
1.0
4.1
Figures
1, 3, 4
1.8 r 0.15
1.5
8.2
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.0
16.4
Figures
5, 7, 8
tPLZ,
tPHZ
Output Disable Time
A to B
CL 30 pF, RL 500:
3.3 r 0.3
0.8
3.5
2.5 r 0.2
1.0
3.8
Figures
1, 3, 4
1.8 r 0.15
1.5
6.8
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.0
13.6
Figures
5, 7, 8
tOSHL,
tOSLH
Output-to-Output Skew
(Note 7)
CL 30 pF, RL 500:
3.3 r 0.3
2.5 r 0.2
1.8 r 0.15
0.5
0.5
ns
0.75
CL 15 pF, RL 2k:
Note 6: For CL 50pF, add approximately 300ps to the AC maximum specification.
1.5 r 0.1
1.5
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VCX162245.PDF ] | |
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