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74VCX16244 PDF даташит

Спецификация 74VCX16244 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs».

Детали детали

Номер произв 74VCX16244
Описание Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VCX16244 Даташит, Описание, Даташиты
www.DataSheet4U.com
October 1996
Revised June 2005
74VCX16244
Low Voltage 16-Bit Buffer/Line Driver with
3.6V Tolerant Inputs and Outputs
General Description
The VCX16244 contains sixteen non-inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74VCX16244 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
2.5 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
r24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model ! 2000V
Machine model ! 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16244G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX16244MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: Ordering Code “G” indicates Tray.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation DS012168
www.fairchildsemi.com









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74VCX16244 Даташит, Описание, Даташиты
Logic Symbol
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
www.fairchildsemi.com
Pin Descriptions
Pin Names
OEn
I0I15
O0O15
NC
Description
Output Enable Input (Active LOW)
Inputs
Outputs
No Connect
FBGA Pin Assignments
12
A O0 NC
B O2 O1
C O4 O3
D O6 O5
E O8 O7
F O10 O9
G O12 O11
H O14 O13
J O15 NC
Truth Tables
3
OE1
NC
VCC
GND
GND
GND
VCC
NC
OE4
4
OE2
NC
VCC
GND
GND
GND
VCC
NC
OE3
5
NC
I1
I3
I5
I7
I9
I11
I13
NC
6
I0
I2
I4
I6
I8
I10
I12
I14
I15
Inputs
OE1
L
L
H
I0–I3
L
H
X
Outputs
O0–O3
L
H
Z
Inputs
OE3
L
L
H
I8-I11
L
H
X
Outputs
O8–O11
L
H
Z
Inputs
OE2
L
L
H
I4-I7
L
H
X
Outputs
O4-O7
L
H
Z
Inputs
Outputs
OE4
I12-I15
O12-O15
LL
L
LH
H
HX
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, inputs may not float)
Z High Impedance
Z
2









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74VCX16244 Даташит, Описание, Даташиты
Functional Description
The 74VCX16244 contains sixteen non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dent of each other. The control pins may be shorted
together to obtain full 16-bit operation.The 3-STATE out-
Logic Diagram
puts are controlled by an Output Enable (OEn) input. When
OEn is LOW, the outputs are in the 2-state mode. When
OEn is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs.
3 www.fairchildsemi.com










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