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74VCX32244 PDF даташит

Спецификация 74VCX32244 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 32-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs».

Детали детали

Номер произв 74VCX32244
Описание Low Voltage 32-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VCX32244 Даташит, Описание, Даташиты
www.DataSheet4U.com
September 2000
Revised November 2002
74VCX32244
Low Voltage 32-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32244 contains thirty-two non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for 8-bit, 16-bit or full 32-bit operation.
The 74VCX32244 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX32244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
2.5 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Packages in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX32244G
(Note 2)(Note 3)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500416
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74VCX32244 Даташит, Описание, Даташиты
Connection Diagram
(Top Thru View)
Pin Descriptions
Pin Names
Description
OEn
I0I31
O0O31
Output Enable Input (Active LOW)
Inputs
Outputs
FBGA Pin Assignments
123456
A O1 O0 OE1 OE2 I0
I1
B O3 O2 GND GND I2
I3
C O5 O4 VCC VCC I4
I5
D O7 O6 GND GND I6
I7
E O9 O8 GND GND I8
I9
F O11 O10 VCC VCC I10 I11
G O13 O12 GND GND I12 I13
H O14 O15 OE4 OE3 I15 I14
J O17 O16 OE5 OE6 I16 I17
K O19 018 GND GND I18 I19
L
O21 O20 VCC VCC
I20
I21
M O23 O22 GND GND I22 I23
N O25 O24 GND GND I24 I25
P
O27 O26 VCC VCC
I26
I27
R O29 O28 GND GND I28 I29
T O30 O31 OE8 OE7 I31 I30
Truth Tables
Inputs
OE1
L
L
H
I0-I3
L
H
X
Outputs
O0-O3
L
H
Z
Inputs
OE2
L
L
H
I4-I7
L
H
X
Outputs
O4-O7
L
H
Z
Inputs
OE3
L
L
H
I8-I11
L
H
X
Outputs
O8–O11
L
H
Z
Inputs
OE4
L
L
H
I12-I15
L
H
X
Outputs
O12-O15
L
H
Z
Inputs
OE5
L
L
H
I16-I19
L
H
X
Outputs
O16-O19
L
H
Z
Inputs
OE6
L
L
H
I20-I23
L
H
X
Outputs
O20-O23
L
H
Z
Inputs
OE7
L
L
H
I24-I27
L
H
X
Outputs
O24-O27
L
H
Z
Inputs
Outputs
OE8
I28-I31
O28-O31
LL
L
LH
H
HX
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
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74VCX32244 Даташит, Описание, Даташиты
Functional Description
The 74VCX32244 contains thirty-two non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dent of each other. The control pins may be shorted
together to obtain full 32-bit operation.The 3-STATE out-
Logic Diagrams
puts are controlled by an Output Enable (OEn) input. When
OEn is LOW, the outputs are in the 2-state mode. When
OEn is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs.
Byte 1
Byte 2
Byte 3
Byte 4
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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