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74VCX32373 PDF даташит

Спецификация 74VCX32373 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary)».

Детали детали

Номер произв 74VCX32373
Описание Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary)
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VCX32373 Даташит, Описание, Даташиты
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Preliminary
February 2001
Revised August 2001
74VCX32373
Low Voltage 32-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs (Preliminary)
General Description
The VCX32373 contains thirty-two non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The 74VCX32373 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX32373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (In to On)
3.0 ns max for 3.0V to 3.6V VCC
3.4 ns max for 2.3V to 2.7V VCC
6.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Support live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Ordering Number Package Number
Package Description
74VCX32373GX
(Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
Note 2: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500567
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74VCX32373 Даташит, Описание, Даташиты
Connection Diagram
Pin Assignment for FBGA
(Top Thru View)
Truth Tables
Inputs
LE1 OE1 I0–I7
XHX
HL L
HLH
LLX
Inputs
LE2
OE2
I8–I15
XHX
HL L
HLH
LLX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Outputs
O0–O7
Z
L
H
O0
Outputs
O8–O15
Z
L
H
O0
Preliminary
Pin Descriptions
Pin Names
Description
OEn
LEn
I0I31
O0O31
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
FBGA Pin Assignments
123456
A O1 O0 OE1 LE1 I0
I1
B O3 O2 GND GND I2
I3
C O5 O4 VCC VCC I4
I5
D O7 O6 GND GND I6
I7
E O9 O8 GND GND I8
I9
F O11 O10 VCC VCC I10 I11
G O13 O12 GND GND I12 I13
H
O14 O15 OE2 LE2
I15
I14
J
O17 O16 OE3 LE3
I16
I17
K O19 O18 GND GND I18 I19
L
O21
O20 VCC VCC
I20
I21
M O23 O22 GND GND I22 I23
N O25 O24 GND GND I24 I25
P
O27
O26 VCC VCC
I26
I27
R O29 O28 GND GND I28 I29
T
O30 O31 OE4 LE4
I31
I30
Inputs
LE3
OE3
I16–I23
XHX
HL L
HLH
LLX
Inputs
LE4
OE4
I24–I31
XHX
HL L
HLH
LLX
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of Latch Enable
Outputs
O16–O23
Z
L
H
O0
Outputs
O24–O31
Z
L
H
O0
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74VCX32373 Даташит, Описание, Даташиты
Preliminary
Functional Description
The 74VCX32373 contains thirty-two edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The 3-
STATE outputs are controlled by the Output Enable (OEn)
input. When OEn is LOW the standard outputs are in the 2-
state mode. When OEn is HIGH, the standard outputs are
in the high impedance mode but this does not interfere with
entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Номер в каталогеОписаниеПроизводители
74VCX32373Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary)Fairchild Semiconductor
Fairchild Semiconductor
74VCX32374Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and OutputsFairchild Semiconductor
Fairchild Semiconductor

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