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PDF 74VCXH162244 Data sheet ( Hoja de datos )
| Número de pieza | 74VCXH162244 | |
| Descripción | Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26W Series Resistor in Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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January 2000
Revised March 2000
74VCXH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26Ω Series Resistor in Outputs
General Description
The VCXH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation. .
The VCXH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74VCXH162244 is also designed with 26Ω series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74VCXH162244 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74VCXH162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s 26Ω series resistors in outputs
s tPD
3.3 ns max for 3.0V to 3.6V VCC
3.8 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
s Static Drive (IOH/IOL)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package
Number
Package Description
74VCXH162244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74VCXH162244MTX
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2000 Fairchild Semiconductor Corporation DS500231
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 14)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5V ± 0.2V
VCC = 1.8V ± 0.15V
Units
Min Max Min Max Min Max
tPHL, tPLH Prop Delay
0.8 3.3 1.0 3.8 1.5 7.6 ns
tPZL, tPZH Output Enable Time
0.8 3.8 1.0 5.1 1.5 9.8 ns
tPLZ, tPHZ Output Disable Time
0.8 3.6 1.0 4.0 1.5 7.2 ns
tOSHL
tOSLH
Output to Output Skew
(Note 15)
0.5 0.5 0.75 ns
Note 14: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
VOHV
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC TA = +25°C Units
(V) Typical
1.8 0.15
2.5 0.25
V
3.3 0.35
1.8 −0.15
2.5 −0.25
V
3.3 −0.35
1.8 1.55
2.5 2.05
V
3.3 2.65
Capacitance
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = 1.8, 2.5V or 3.3V, VI = 0V or VCC
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V
TA = +25°C
Typical
6
7
20
Units
pF
pF
pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VCXH162244.PDF ] | |
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