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PDF 74VHC14 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC14 | |
| Descripción | Hex Schmitt Inverter | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 2015
74VHC14
Hex Schmitt Inverter
Features
• High Speed: tPD = 5.5 ns (Typ.) at VCC = 5 V
• Low Power Dissipation: ICC = 2 μA (Max.) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC (Min.)
• Power down protection is provided on all inputs
• Low Noise: VOLP = 0.8 V (Max.)
• Pin and Function Compatible with 74HC14
General Description
The VHC14 is an advanced high speed CMOS Hex
Schmitt Inverter fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. Pin configuration and func-
tion are the same as the VHC04 but the inputs have hys-
teresis between the positive-going and negative-going
input thresholds, which are capable of transforming
slowly changing input signals into sharply defined, jitter-
free output signals, thus providing greater noise margin
than conventional inverters.
An input protection circuit ensures that 0 V to 7 V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5 V to 3 V sys-
tems and two supply systems such as battery back up.
This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Part Number
74VHC14M
74VHC14MX
74VHC14SJX
74VHC14MTC
74VHC14MTCX
Top Mark
74VHC14
74VHC14
VHC14
V14
V14
Package
SOIC 14L
SOIC 14L
SOP 14L
TSSOP 14L
TSSOP 14L
Packing Method
Rail
Tape and Reel
Tape and Reel
Rail
Tape and Reel
© 1993 Fairchild Semiconductor Corporation
74VHC14 Rev. 1.5
www.fairchildsemi.com
1 page  
Physical Dimensions
14
6.00
8.75
8.50
7.62
A
8
B
4.00
3.80
0.65
5.60
PIN ONE
INDICATOR
1
1.27
(0.33)
7
0.51
0.35
1.70 1.27
LAND PATTERN RECOMMENDATION
0.25 M C B A
1.75 MAX
1.50
1.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
SEE DETAIL A
0.25
0.10 C
0.10 C
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
X 45°
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE FLASH OR BURRS.
D) LANDPATTERN STANDARD:
0.36
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-LEAD, SOIC, JEDEC MS-012, 0.150 INCH, NARROW BODY
© 1993 Fairchild Semiconductor Corporation
74VHC14 Rev. 1.5
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74VHC14.PDF ] | |
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