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74VHC273M PDF даташит

Спецификация 74VHC273M изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Octal D-Type Flip-Flop».

Детали детали

Номер произв 74VHC273M
Описание Octal D-Type Flip-Flop
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VHC273M Даташит, Описание, Даташиты
April 1994
Revised April 1999
74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal D-
type flip-flop fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: fMAX= 165 MHz (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.9V (max)
s Pin and function compatible with 74HC273
Ordering Code:
Order Number Package Number
Package Description
74VHC273M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
© 1999 Fairchild Semiconductor Corporation DS011670.prf
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74VHC273M Даташит, Описание, Даташиты
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Operating Mode
Reset (Clear)
Load ’1’
Load ’0’
MR
L
H
H
Inputs
CP
X


Outputs
Dn Qn
XL
HH
LL
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC273M Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Input Diode Current (IIK)
Output Diode Current (IOK)
DC Output Current (IOUT)
DC VCC/GND Current (ICC)
Storage Temperature (TSTG)
Lead Temperature (TL)
(Soldering, 10 seconds)
0.5V to +7.0V
0.5V to +7.0V
0.5V to VCC + 0.5V
20 mA
±20 mA
±25 mA
±75 mA
65°C to +150°C
260°C
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC)
2.0V to +5.5V
Input Voltage (VIN)
0V to +5.5V
Output Voltage (VOUT)
0V to VCC
Operating Temperature (TOPR)
40°C to +85°C
Input Rise and Fall Time (tr, tf)
VCC = 3.3V ± 0.3V
0 ns/V 100 ns/V
VCC = 5.0V ± 0.5V
0 ns/V 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input
Voltage
VIL LOW Level Input
Voltage
VOH HIGH Level Output
Voltage
VOL LOW Level Output
Voltage
IIN Input Leakage
Current
ICC Quiescent Supply
Current
VCC
(V)
2.0
3.0 5.5
2.0
3.0 5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
0 5.5
Min
1.50
0.7 VCC
1.9
2.9
4.4
2.58
3.94
TA = 25°C
Typ
2.0
3.0
4.5
0.0
0.0
0.0
Max
0.50
0.3 VCC
0.1
0.1
0.1
0.36
0.36
±0.1
TA = −40°C to +85°C
Min Max
1.50
0.7 VCC
0.50
0.3 VCC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
Units
Conditions
V
V
VIN = VIH IOH = −50 µA
V or VIL
V IOH = −4 mA
IOH = −8 mA
VIN = VIH IOL = 50 µA
V or VIL
V IOL = 4 mA
IOL = 8 mA
µA VIN = 5.5V or GND
5.5
4.0
40.0
µA VIN = VCC or GND
Noise Characteristics
Symbol
Parameter
VOLP
(Note 3)
Quiet Output Maximum Dynamic VOL
VOLV
(Note 3)
Quiet Output Minimum Dynamic VOL
VIHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage
VILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage
Note 3: Parameter guaranteed by design.
VCC
(V)
5.0
5.0
5.0
5.0
TA = 25°C
Typ Limits
0.6 0.9
0.6
0.9
3.5
1.5
Units
V
V
V
V
Conditions
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
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