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SDA3302 PDF даташит

Спецификация SDA3302 изготовлена ​​​​«Siemens» и имеет функцию, называемую «GHz PLL with I2C Bus and Four Chip Addresses».

Детали детали

Номер произв SDA3302
Описание GHz PLL with I2C Bus and Four Chip Addresses
Производители Siemens
логотип Siemens логотип 

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SDA3302 Даташит, Описание, Даташиты
GHz PLL with I2C Bus
and Four Chip Addresses
Preliminary Data
Features
q 1-chip system for MPU
control (I2C bus)
q 4 programmable chip addresses
q Short pull-in time for quick channel
switch-over and optimized loop
stability
q Charge pump output with switch
off option
q Up to 3*) high current band switch
outputs (20 mA)
q Up to 4*) output ports (5 mA)
*) depending on version
P-DIP-18-5
P-DSO-16-1
SDA 3302 Family
Bipolar IC
P-DSO-20-1
Type
SDA 3302-5
SDA 3302-5X
SDA 3302-5X6
SDA 3302-5X
SDA 3302-5X6
Ordering Code
Q67000-H5112
Q67000-H5111
Q67000-H5110
Q67006-H5111
Q67006-H5110
Package
P-DIP-18-5
P-DSO-20-1 (SMD)
P-DSO-16-1 (SMD)
P-DSO-20-1 Tape & Reel (SMD)
P-DSO-16-1 Tape & Reel (SMD)
Semiconductor Group
1
02.97









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SDA3302 Даташит, Описание, Даташиты
SDA 3302 Family
Functional Description
Combined with a VCO (tuner) the SDA 3302 device, with four hardware-switched chip
addresses, forms a digitally programmable phase-locked loop for use in television sets with
PLL frequency-synthesis tuning.
The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillators
between 16 and 1300 MHz in increments of 62.5 kHz. The tuning process is controlled by a
microprocessor via an I2C bus. The crystal oscillator generates a sinusoidal signal suppressing
the higher-order harmonics, which reduces the moiré noise considerably.
Circuit Description
Tuning Section (refer to block diagram)
UHF/VHF
REF
Q1, Q2
The tuner signal is capacitively coupled at the UHF/VHF input and
subsequently amplified. The reference input REF should be decoupled to
ground using a capacitor of low series inductance. The signal passes
through an asynchronous divider with a fixed ratio of P = 8, an adjustable
divider with ratio N = 256 through 32767 and is then compared in a digital
phase/frequency detector to a reference frequency fREF of 7.8125 kHz. The
latter is derived from a balanced, low-impedance 4 MHz crystal oscillator
(pin Q1, Q2), whose output signal is divided by Q = 512.
The phase detector has two outputs UP and DOWN that drive the two current
sources I+ and I– of a charge pump. If the negative edge of the divided VCO
signal appears prior to the negative edge of the reference signal, the I+
current source pulses for the duration of the phase difference. In the reverse
case the I– current source pulses.
PD, UD
When the two signals are in phase, the charge-pump output (PD) goes high-
impedance (PLL is locked). An active low-pass filter integrates the current
pulses to generate the tuning voltage for the VCO (internal amplifier an
external transistor at the UD output and an external RC circuitry). The
charge-pump output can also be set to high-impedance state when control
bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter
over a long period in the high-impedance state as a result of self-discharge
in the peripheral circuitry. UD can be disconnected internally by the control
bit OS to enable external adjustments.
By means of a control bit 5I the pump current can be switched between two
values by software. This switchover permits alteration of the control
response of the PLL in the locked-in state. In this way different VCO gains in
the different TV bands can be compensated for example.
Semiconductor Group
2









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SDA3302 Даташит, Описание, Даташиты
SDA 3302 Family
Circuit Description (cont’d)
P0-P2
P4-P7
CAS
The software-switched outputs (P0, P1, P2) can be used for direct band
selection (20-mA current output).
P4, P5, P6 and P7 are open-collector outputs for a variety of different
purposes. The test bit T1 = 1 switches the test signals f REF (4 MHz/512) and
Cy (divided input signal) to P6 and P7.
Four different chip addresses can be set by appropriate connection of pin
CAS.
I2C-Bus Interface
SCL, SDA
Data are exchanged between the processor and the PLL on the I2C bus. The
clock is produced by the processor (input SCL), while pin SDA works as an
input or output depending on the direction of the data (open collector;
external pullup resistor). Both inputs have hysteresis and a lowpass
characteristic, which enhances the noise immunity of the I2C bus.
The data from the processor are applied to an I2C bus controller and filed in
registers according to their function. When the bus is free, both lines are in
the marking state (SDA, SCL are high). Each telegram begins with a start
condition and ends with the stop condition. Start condition: SDA goes low
while SCL remains high; stop condition: SDA goes high while SCL remains
high. All further data exchanges occur while SCL is low and are accepted by
the controller with the positive clock edge.
For what follows, refer to the table of logic allocations.
All telegrams are transmitted byte by byte, followed by a ninth clock pulse,
during which the controller puts the SDA line on low (acknowledge condition).
The first byte consists of seven address bits, with which the processor
selects the PLL from a number of peripheral devices (chip select). The eighth
bit is always low. In the data portion of the telegram the first bit of the first or
third data byte determines whether a divider ratio or control information
follows. In each case the byte following the first byte must be of the same
data type (or a stop condition).
VS, GND
When the supply voltage is applied, a power-on reset circuit prevents the PLL
from putting the SDA line on low, which would block the bus.
Semiconductor Group
3










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Номер в каталогеОписаниеПроизводители
SDA3302GHz PLL with I2C Bus and Four Chip AddressesSiemens
Siemens

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