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PDF SDA9220-5 Data sheet ( Hoja de datos )
| Número de pieza | SDA9220-5 | |
| Descripción | Memory Sync Controller III | |
| Fabricantes | Siemens | |
| Logotipo |  |
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Memory Sync Controller III
SDA 9220-5
Preliminary Data
Features
q Large area flicker elimination through field doubling
q Additional elimination of interline flicker in field mode
q Field switching and selection in field mode
q Noise and cross-color reduction
q Stills
q 9-image display, still-in-picture, picture-in-still
with different frame versions
q Zoom with selection of enlarged picture segment
(8 x 12 positions)
q Pin-programmable operation without standard
conversion
P-LCC-44-1
MOS IC
Type
SDA 9220-5
Ordering Code
Q67100-H5087
Package
P-LCC-44-1 (SMD)
Functional Description
The MSC III is a component of the TV-SAM Featurebox and is responsible for driving the picture
memory devices (TV-SAMs) and generating sync signals (figure 6). Together with the other
devices of the Featurebox it enhances picture quality and offers a number of special operating
modes.
The MSC III is set via the I2C Bus, it being possible to switch the I2C Bus address by hardware so
that implementation of a simple frame Featurebox is possible in conjunction with the signal MUX
supplied by the MSC III.
Other major output signals of the SDA 9220-5, in addition to the clocks LL3X (13.5 MHz) and LL1.5X
(27 MHz), are the memory-driving signals (RA, RB, WT, RE, SCAD, SCA) and the sync signal CSY
for the teletext device. The horizontal sync signals (HS2, BLN2) and the vertical sync signals (VS1,
VS2) are also generated.
Semiconductor Group
117
01.94
1 page  
SDA 9220-5
q When switching from free running to line-locked mode, the following maximum synchronization
times can occur for standard signals:
a) Vertical synchronization at
50 (60) Hz and 100 (120) Hz:
220 (183) ms
a) Horizontal synchronization at
50 (60) Hz:
100 (83) ms
100 (120) Hz:
100 (75) ms
Device Interfaces
The interfaces of this device are designed to work with the CSG SDA 9257 and triple ADC
SDA 9205-2, or DMSD/CGC, the TV-SAMs SDA 9251-2X and Picture Processor SDA 9290-5. The
standard conversion function can be enabled and disabled on one pin. All other functions are set on
an I2C Bus interface.
I2C Bus Interface
1. Functional Overview
The following control signals are received on the I2C Bus:
– Synchronization (EXSYN)
– Blanking (BLK)
– Control for frame mode (MUXI, MUXS)
– VS noise reduction (VNR)
– 50/60-Hz standard (VERT)
– Deflection raster (VDM 1-0)
– Field mode with field changeover (FLDM, FLDC, FLDF)
– Delay compensation for write channel (WDEL 4-0)
– Still (STB)
– Frame (FR)
– Write mode (WM 1-0)
– Picture position for 9-image, picture-in-picture (VPOS 1-0, HPOS 1-0)
– Zoom mode (ZM)
– Position of zoom detail (ZV 2-0, ZH 3-0)
– NTSC mode with 864 pixels per line (N864)
– HS2 phase relation (HP 6-0)
– Disabling of frame display signal (FRDIS)
– Delay of frame display signal (FRD 6-0)
– Duration of CFH signal (CFHW 3-0)
– Position of CFH signal (CFHP 3-0)
Semiconductor Group
121
5 Page 
SDA 9220-5
FRM Delay (subaddress 05)
FRM Disable
Frame display signal FRM enable
Frame display signal FRM disable (FRM = L)
Control Bit FRDIS (D7)
0
1
Delay for Frame
Display Signal
0 LL1.5 cycles
to
127 LL1.5 cycles
FRD 6
(D6)
0
FRD 5
(D5)
0
Control Bit
FRD 4 FRD 3 FRD 2
(D4) (D3) (D2)
000
FRD 1
(D1)
0
FRD 0
(D0)
0
1111111
CFH Control (subaddress 06)
CFH Width (H level)
0 halfline
to
15 halflines
CFHW3
(D7)
0
1
Control Bit
CFHW2
(D6)
CFHW1
(D5)
00
11
CFHW0
(D4)
0
1
CFH Position Before VS
3 halflines
to
18 halflines
CFHP3
(D3)
0
1
Control Bit
CFHP2
(D2)
CFHP1
(D1)
00
11
CFHP0
(D0)
0
1
Semiconductor Group
127
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SDA9220-5.PDF ] | |
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