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PDF SDA9362 Data sheet ( Hoja de datos )
| Número de pieza | SDA9362 | |
| Descripción | DDC-PLUS-Deflection Controller | |
| Fabricantes | Siemens | |
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ICs for Consumer Electronics
DDC-PLUS-Deflection Controller
SDA 9362
Data Sheet 1998-02-01
1 page  
DDC-PLUS-Deflection Controller
SDA 9362
MOS
1 Overview
1.1 Features
• Deflection - Protection - 16:9 / 4:3
• Ι2C Bus alignment of all deflection parameters
• All EW-, V- and H-functions (incl. Φ2)
• PW EHT compensation
• PH EHT compensation
P-MQFP-44-2
• Compensation of H-phase deviation
(e.g. caused by white bar)
• Upper/lower EW-corner correction separately adjustable
• V-angle correction: Vertical frequent linear modulation of H-phase
• V-bow correction: Vertical frequent parabolic modulation of H-phase
• Three reduced V-scan modes (75 %, 66 %, 50 % V-size) selectable
• H- and V-blanking time adjustable
• Partial overscan adjustable to hide the cut off control measuring lines in the reduced
scan modes
• Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different
letterbox formats without annoying overscan
• Dynamic PH EHT-compensation (white bar)
• Self adaptation of V-frequency/number of lines per field between 192 and 680 for each
possible line frequency
• Protection against EHT run away (X-rays protection)
• Protection against missing V-deflection (CRT-protection)
• Two digital outputs for general purpose, controlled by Ι2C Bus
• Selectable softstart of the H-output stage
• P-MQFP-44-2 package
• 5 V supply voltage
Type
SDA 9362
Semiconductor Group
Ordering Code
Q67101-H5173-A701
5
Package
P-MQFP-44-2
1998-02-01
5 Page 
SDA 9362
VPROT:
Vertical sawtooth voltage
Vi < V1 in first half of V-period or
Vi > V2 in second half: HD disabled
The pin SCP delivers the composite blanking signal SCP. It contains burst (Vb), H-
blanking HBL (VHBL) and selectable V-blanking (control bit SSC). The phase of the H-
blanking period can be varied by Ι2C Bus. For the timing following settings are possible:
BD = 1
BD = 0, BSE = 0 (default value)
BD = 0, BSE = 1(alignment range)
SSC = 0
SSC = 1
: tBL = 0
: tHBL = tf (H-flyback time)
: tHBL = (4 * H-blanking-time + 1) / CLL
: tDBL = (H-shift + 4 * H-blanking-phase
-2 * H-blanking-time + 43) / CLL
: tBL = tVBL during V-blanking period
: tBL is always tHBL
Input Signal
HSYNC
VOH
VOHBL
VOL
t DB
t DBL
tB
t BL
UED10260
Figure 3
BG-pulse width tB
Delay to HSYNC tDB
54 / CLL
36 / CLL
Semiconductor Group
11
1998-02-01
11 Page | ||
| Páginas | Total 39 Páginas | |
| PDF Descargar | [ Datasheet SDA9362.PDF ] | |
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