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74VHC4316N PDF даташит

Спецификация 74VHC4316N изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Quad Analog Switch with Level Translator».

Детали детали

Номер произв 74VHC4316N
Описание Quad Analog Switch with Level Translator
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VHC4316N Даташит, Описание, Даташиты
April 1994
Revised April 1999
74VHC4316
Quad Analog Switch with Level Translator
General Description
These devices are digitally controlled analog switches
implemented in advanced silicon-gate CMOS technology.
These switches have low “on” resistance and low “off” leak-
ages. They are bidirectional switches, thus any analog
input may be used as an output and vice-versa. Three sup-
ply pins are provided on the 4316 to implement a level
translator which enables this circuit to operate with 0V–6V
logic levels and up to ±6V analog switch levels. The 4316
also has a common enable input in addition to each
switch's control which when HIGH will disable all switches
to their off state. All analog inputs and outputs and digital
inputs are protected from electrostatic damage by diodes
to VCC and ground.
Features
s Typical switch enable time: 20 ns
s Wide analog input voltage range: ±6V
s Low “on” resistance: 50 typ. (VCCVEE = 4.5V)
30 typ. (VCCVEE = 9V)
s Low quiescent current: 80 µA maximum (74VHC)
s Matched switch characteristics
s Individual switch controls plus a common enable
s Pin functional compatible with 74HC4316
Ordering Code:
Order Number
74VHC4316M
74VHC4316WM
74VHC4316MTC
74VHC4316N
Package Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Truth Table
Connection Diagram
Inputs
E CTL
HX
LL
LH
Switch
I/O–O/I
“OFF”
“OFF”
“ON”
Logic Diagram
Top View
© 1999 Fairchild Semiconductor Corporation DS011678.prf
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74VHC4316N Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC)
Supply Voltage (VEE)
DC Control Input Voltage (VIN)
DC Switch I/O Voltage (VIO)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to +7.5V
+0.5 to 7.5V
1.5 to VCC+1.5V
VEE0.5 to VCC+0.5V
±20 mA
±25 mA
±50 mA
65°C to +150°C
600 mW
500 mW
260°C
Min Max Units
Supply Voltage (VCC)
Supply Voltage (VEE)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
2
0
0
40
6
6
VCC
+85
V
V
V
°C
(tr, tf)
VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
VCC = 12.0V
250 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VEE
VCC
TA = 25°C
TA = −40°C to +85°C Units
Typ Guaranteed Limits
VIH Minimum HIGH
Level Input
2.0V
4.5V
1.5
3.15
1.5
3.15
V
Voltage
6.0V
4.2 4.2
VIL Maximum LOW
Level Input
2.0V
4.5V
0.5
1.35
0.5
1.35
V
Voltage
6.0V
1.8 1.8
RON
Minimum “ON”
VCTL = VIH,
GND
4.5V
100
170
200
Resistance
IS = 2.0 mA
4.5V
4.5V
40
85
105
(Note 5)
VIS = VCC to VEE
6.0V
6.0V
30
70
85
(Figure 1)
VCTL = VIH,
IS = 2.0 mA
VIS = VCC or VEE
(Figure 1)
GND
GND
4.5V
6.0V
2.0V
4.5V
4.5V
6.0V
100
40
50
20
180
80
60
40
215
100
75
60
RON
Maximum “ON”
Resistance
Matching
VCTL = VIH
VIS = VCC to VEE
GND
4.5V
6.0V
4.5V
4.5V
6.0V
10
5
5
15
10
10
20
15
15
IIN
Maximum Control
VIN = VCC or GND
GND
6.0V
Input Current
±0.1
±1.0
µA
IIZ
Maximum Switch
VOS = VCC or VEE
“OFF” Leakage
VIS = VEE or VCC
GND
6.0V
Current
VCTL = VIL
6.0V
6.0V
(Figure 2)
±30
±300
nA
±50 ±500
IIZ
Maximum Switch
VIS = VCC to VEE
“ON” Leakage
VCTL = VIH,
Current
VOS = OPEN
(Figure 3)
GND
6.0V
6.0V
6.0V
±20 ±75 nA
±30 ±150
ICC
Maximum Quiescent
VIN = VCC or GND
GND
6.0V
1.0 10 µA
Supply Current
IOUT = 0 µA
6.0V
6.0V
4.0 40
Note 4: For a power supply of 5V ±10% the worst case on resistances (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (VCC–VEE) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
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74VHC4316N Даташит, Описание, Даташиты
AC Electrical Characteristics
VCC = 2.0V 6.0V, VEE = 0V 6V, CL = 50 pF unless otherwise specified
Symbol
Parameter
Conditions
VEE
tPHL, tPLH
Maximum Propagation
Delay Switch In to
Out
tPZL, tPZH
Maximum Switch Turn
“ON” Delay
(Control)
RL = 1 k
tPHZ, tPLZ
Maximum Switch Turn
“OFF” Delay
(Control)
RL = 1 k
tPZL, tPZH
Maximum Switch
Turn “ON” Delay
(Enable)
tPLZ, tPHZ
Maximum Switch
Turn “OFF” Delay
(Enable)
Minimum Frequency
Response (Figure 7)
20 log (VOS/VIS)= −3 dB
Control to Switch
Feedthrough Noise
(Figure 8)
RL = 600, VIS = 2VPP
at (VCC–VEE/2)
(Note 6)(Note 7)
RL = 600, f = 1 MHz
CL = 50 pF
(Note 7)(Note 8)
Crosstalk Between
any Two Switches
RL = 600, f = 1 MHz
(Figure 9)
Switch OFF Signal
Feedthrough
Isolation
RL = 600, f = 1 MHz
VCTL = VIL
(Figure 10)
(Note 7)(Note 8)
THD
Sinewave Harmonic
Distortion
RL = 10 K, CL = 50 pF,
f = 1 KHz
(Figure 11)
CIN Maximum Control
Input Capacitance
VIS = 4 VPP
VIS = 8 VPP
CIN Maximum Switch
Input Capacitance
CIN Maximum Feedthrough VCTL = GND
Capacitance
CPD Power Dissipation
Capacitance
Note 6: Adjust 0 dBm for f = 1 kHz (Null RL/Ron Attenuation).
Note 7: VIS is centered at VCC–VEE/2.
Note 8: Adjust for 0 dBm.
GND
GND
4.5V
6.0V
GND
GND
4.5V
6.0V
GND
GND
4.5V
6.0V
GND
GND
4.5V
6.0V
GND
GND
4.5V
6.0V
0V
4.5V
0V
4.5V
0V
4.5V
0V
4.5V
0V
4.5V
VCC
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
4.5
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
TA=+25°C
TA=−40°C to +85°C
Typ Guaranteed Limits
15 30
37
5 10
13
48
12
37
11
25 97
120
20 35
43
15 32
39
14 30
37
35 145
180
25 50
63
20 44
55
20 44
55
27 120
150
20 41
52
19 38
48
18 36
45
42 155
190
28 53
67
23 47
59
21 47
59
40
100
Units
ns
ns
ns
ns
ns
MHz
100
250 mV
52
50 dB
42 dB
44
0.013
0.008
5
35
0.5
15
%
pF
pF
pF
pF
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