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74VHC573 PDF даташит

Спецификация 74VHC573 изготовлена ​​​​«STMicroelectronics» и имеет функцию, называемую «OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING».

Детали детали

Номер произв 74VHC573
Описание OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
Производители STMicroelectronics
логотип STMicroelectronics логотип 

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74VHC573 Даташит, Описание, Даташиты
® 74VHC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHC573 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
While the LE input is held at a high level, the Q
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC573M
74VHC573T
outputs will follow the data inputs precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
June 1999
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74VHC573 Даташит, Описание, Даташиты
74VHC573
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 3, 4,
5, 6, 7,
8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
S Y M B OL
OE
D0 to D7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
Q0 to Q7 3 State Latch Outputs
LE
GND
VCC
Latch Enable
Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE LE
HX
LL
LH
LH
X:Don’t care
Z: High impedance
* Q outputs are latched atthe time when the LEinput is taken low logic level.
D
X
X
L
H
OUT PUTS
Q
Z
NO CHANGE *
L
H
LOGIC DIAGRAM
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74VHC573 Даташит, Описание, Даташиты
74VHC573
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC Supply Voltage
-0.5 to +7.0
V
VI DC Input Voltage
-0.5 to +7.0
V
VO DC Output Voltage
-0.5 to VCC + 0.5
V
IIK DC Input Diode Current
- 20 mA
IOK DC Output Diode Current
± 20 mA
IO DC Output Current
± 25 mA
ICC or IGND DC VCC or Ground Current
± 75 mA
Tstg Storage Temperature
-65 to +150
oC
TL Lead Temperature (10 sec)
300 oC
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC Supply Voltage
VI Input Voltage
VO Output Voltage
Top Operating Temperature
dt/dv Input Rise and Fall Time (see note 1) (VCC = 3.3 ± 0.3V)
(V CC = 5.0 ± 0.5V)
1) VIN from 30% to70%of VCC
Valu e
2.0 to 5.5
0 to 5.5
0 to VCC
-40 to +85
0 to 100
0 to 20
Unit
V
V
V
oC
ns/V
ns/V
DC SPECIFICATIONS
Symb ol
Parameter
VIH High Level Input
Voltage
VIL Low Level Input
Voltage
VOH High Level Output
Voltage
VOL Low Level Output
Voltage
IOZ High Impedance
Output Leakage
Current
II Input Leakage Current
ICC Quiescent Supply
Current
Test Conditions
V CC
( V)
2 .0
3.0 to 5.5
2.0
3.0 to 5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4 .5
3.0
4.5
5 .5
IO=-50 µA
IO=-50 µA
IO=-50 µA
IO=-4 mA
IO=-8 mA
IO=50 µA
IO=50 µA
IO=50 µA
IO=4 mA
IO=8 mA
VI = VIH or VIL
VO = VCC or GND
0 to 5.5
5.5
VI = 5.5V or GND
VI = VCC or GND
Value
TA = 25 oC
-40 to 85 oC
Min. Typ . Max. Min . Max.
1.5 1.5
0.7VCC
0.7VCC
0.5 0.5
0.3VCC
0.3VCC
1.9 2.0
1.9
2.9 3.0
2.9
4.4 4.5
4.4
2.58 2.48
3.94 3.8
0.0 0.1
0.1
0.0 0.1
0.1
0.0 0.1
0.1
0.36 0.44
0.36 0.44
±0.25
±2.5
±0.1
4
±1.0
40
Un it
V
V
V
V
µA
µA
µA
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