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74VHC573N Datasheet Download - Fairchild Semiconductor

Номер произв 74VHC573N
Описание Octal D-Type Latch with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VHC573N Даташит, Описание, Даташиты
March 1993
Revised April 1999
74VHC573
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC573 is an advanced high speed CMOS octal latch
with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type latch is con-
trolled by a latch enable input (LE) and an Output Enable
input (OE). When the OE input is HIGH, the eight outputs
are in a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: tPD = 5.0 ns (typ) at VCC = 5V
s High Noise Immunity: VNIH = VNIL = 28% VCC (Min)
s Power Down Protection is provided on all inputs
s Low Noise: VOLP = 0.6V (typ)
s Low Power Dissipation: ICC = 4 µA (Max) @ TA = 25°C
s Pin and function compatible with 74HC573
Ordering Code:
Order Number Package Number
Package Description
74VHC573M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC573N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011563.prf
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74VHC573N Даташит, Описание, Даташиты
Functional Description
The VHC573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs, a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode, but, this does not interfere with entering
new data into the latches.
Truth Table
Inputs
OE LE
LH
LH
LL
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
D
H
L
X
X
Outputs
On
H
L
O0
Z
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC573N Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Input Diode Current (IIK)
Output Diode Current
DC Output Current (IOUT)
DC VCC/GND Current (ICC)
Storage Temperature (TSTG)
Lead Temperature (TL)
(Soldering, 10 seconds)
0.5V to +7.0V
0.5V to +7.0V
0.5V to VCC +0.5V
20 mA
±20 mA
±25 mA
±75 mA
65°C to +150°C
260°C
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC)
2.0V to +5.5V
Input Voltage (VIN)
0V to +5.5V
Output Voltage (VOUT)
0V to VCC
Operating Temperature (TOPR)
40°C to +85°C
Input Rise and Fall Time (tr, tf)
VCC = 3.3V ± 0.3V
0 100 ns/V
VCC = 5.0V ± 0.5V
0 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
IOZ
IIN
ICC
Parameter
VCC
(V)
HIGH Level Input
2.0
Voltage
3.0 5.5
LOW Level Input
2.0
Voltage
3.0 5.5
HIGH Level Output
2.0
Voltage
3.0
4.5
3.0
4.5
LOW Level Output
2.0
Voltage
3.0
4.5
3.0
4.5
3-STATE Output
5.5
Off-State Current
Input Leakage Current
0 5.5
Quiescent Supply Current 5.5
Min
1.50
0.7 VCC
1.9
2.9
4.4
2.58
3.94
TA = 25°C
Typ
2.0
3.0
4.5
0.0
0.0
0.0
Max
0.50
0.3 VCC
0.1
0.1
0.1
0.36
0.36
±0.25
±0.1
4.0
TA = −40°C to +85°C
Min Max
1.50
0.7 VCC
0.50
0.3 VCC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±2.5
±1.0
40.0
Units
Conditions
V
V
VIN = VIH
V or VIL IOH = −50 µA
V IOH = −4 mA
IOH = −8 mA
VIN = VIH
V or VIL IOL = 50 µA
V IOL = 4 mA
IOL = 8 mA
µA VIN = VIH or VIL
VOUT = VCC or GND
µA VIN = 5.5V or GND
µA VIN = VCC or GND
Noise Characteristics
Symbol
Parameter
VOLP
(Note 3)
Quiet Output Maximum Dynamic VOL
VOLV
(Note 3)
Quiet Output Minimum Dynamic VOL
VIHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage
VILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage
Note 3: Parameter guaranteed by design.
VCC
(V)
5.0
5.0
5.0
5.0
TA = 25°C
Typ Limits
0.9 1.2
0.8
1.0
3.5
1.5
Units
V
V
V
V
Conditions
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
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