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74VHC595 PDF даташит

Спецификация 74VHC595 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «8-Bit Shift Register with Output Latches».

Детали детали

Номер произв 74VHC595
Описание 8-Bit Shift Register with Output Latches
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VHC595 Даташит, Описание, Даташиты
August 1993
Revised April 1999
74VHC595
8-Bit Shift Register with Output Latches
General Description
The VHC595 is an advanced high-speed CMOS Shift Reg-
ister fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has eight 3-STATE outputs. Separate clocks
are provided for both the shift register and the storage reg-
ister. The shift register has a direct-overriding clear, serial
input, and serial output (standard) pins for cascading. Both
the shift register and storage register use positive-edge
triggered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: tPD = 5.4 ns (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.9V (typ)
s Pin and function compatible with 74HC595
Ordering Code:
Order Number Package Number
Package Description
74VHC595M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC595SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC595MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC595N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS011640.prf
www.fairchildsemi.com









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74VHC595 Даташит, Описание, Даташиты
Pin Descriptions
Pin Names
Description
SER
Serial Data Input
SCK
Shift Register Clock Input
(Active rising edge)
RCK
Storage Register Clock Input
(Active rising edge)
SCLR
Reset Input
G 3-STATE Output Enable Input
(Active LOW)
QA - QH
Q’H
Parallel Data Outputs
Serial Data Output
Timing Diagram
Truth Table
Inputs
SER RCK SCK SCLR G
Function
XXX
XXX
XXX
X H QA thru QH 3-STATE
X L QA thru QH outputs enabled
L L Shift Register cleared
LX
QH = 0
H L Shift Register clocked
HX
QN = Qn-1, Q0 = SER = L
H L Shift Register clocked
XX
QN = Qn-1, Q0 = SER = H
H L Contents of Shift
Register transferred to
output latches
www.fairchildsemi.com
2









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74VHC595 Даташит, Описание, Даташиты
Logic Diagram
(positive logic)
3 www.fairchildsemi.com










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