|
|
PDF 74VHC595N Data sheet ( Hoja de datos )
| Número de pieza | 74VHC595N | |
| Descripción | 8-Bit Shift Register with Output Latches | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74VHC595N (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
August 1993
Revised April 1999
74VHC595
8-Bit Shift Register with Output Latches
General Description
The VHC595 is an advanced high-speed CMOS Shift Reg-
ister fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has eight 3-STATE outputs. Separate clocks
are provided for both the shift register and the storage reg-
ister. The shift register has a direct-overriding clear, serial
input, and serial output (standard) pins for cascading. Both
the shift register and storage register use positive-edge
triggered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: tPD = 5.4 ns (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.9V (typ)
s Pin and function compatible with 74HC595
Ordering Code:
Order Number Package Number
Package Description
74VHC595M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC595SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC595MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC595N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS011640.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
Units
(V) Min Typ Max Min Max
Conditions
tPLH Propagation Delay Time 3.3 ± 0.3
tPHL
RCK to QA–QH
5.0 ± 0.5
tPLH Propagation Delay Time 3.3 ± 0.3
tPHL SCK–Q'H
5.0 ± 0.5
tPHL Propagation Delay Time 3.3 ± 0.3
SCLR –Q'H
7.7 11.9 1.0 13.5
ns
10.2 15.4 1.0 17.0
5.4 7.4 1.0 8.5
ns
6.9 9.4 1.0 10.5
8.8 13.0 1.0 15.0
ns
11.3 16.5 1.0 18.5
6.2 8.2 1.0 9.4
ns
7.7 10.2 1.0 11.4
8.4 12.8 1.0 13.7
ns
10.9 16.3 1.0 17.2
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
5.0 ± 0.5
5.9 8.0 1.0 9.1
ns
7.4 10.0 1.0 11.1
CL = 15 pF
CL = 50 pF
tPZL
tPZH
Output Enable Time
G to QA–QH
3.3 ± 0.3
7.5
11.5
1.0
13.5
ns RL = 1 kΩ
CL = 15 pF
9.0 15.0 1.0 17.0
CL = 50 pF
5.0 ± 0.5
4.8 8.6 1.0 10.0
ns
8.3 10.6 1.0 12.0
CL = 15 pF
CL = 50 pF
tPLZ
Output Disable Time
3.3 ± 0.3
tPHZ
G to QA–QH
5.0 ± 0.5
12.1 15.7
1.0
16.2
ns RL = 1 kΩ
CL = 50 pF
7.6 10.3 1.0 11.0
CL = 50 pF
fMAX
Maximum Clock
Frequency
3.3 ± 0.3
80
55
150
130
70 MHz CL = 15 pF
50 CL = 50 pF
5.0 ± 0.5
135
95
185
155
115
MHz
85
CL = 15 pF
CL = 50 pF
tOSLH
tOSHL
Output to Output
Skew
3.3 ± 0.3
5.0 ± 0.5
1.5
1.5 (Note 4)
ns
CL = 50 pF
1.0 1.0
CL = 50 pF
CIN Input Capacitance
5.0 10
10 pF VCC = Open
COUT
Output Capacitance
6.0
pF VCC = 5.0V
CPD Power Dissipation
Capacitance
87
(Note 5)
pF
Note 4: Parameter guaranteed by design. tOSLH = | tPLH max − tPLH min|; tOSHL = | tPHL max − tPHL min|.
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC.
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VHC595N.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74VHC595 | 8-Bit Shift Register with Output Latches | Fairchild Semiconductor |
| 74VHC595M | 8-Bit Shift Register with Output Latches | Fairchild Semiconductor |
| 74VHC595MTC | 8-Bit Shift Register with Output Latches | Fairchild Semiconductor |
| 74VHC595N | 8-Bit Shift Register with Output Latches | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |