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74VHC74 Datasheet Download - STMicroelectronics

Номер произв 74VHC74
Описание DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
Производители STMicroelectronics
логотип STMicroelectronics логотип 

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74VHC74 Даташит, Описание, Даташиты
® 74VHC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
fMAX =170 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
technology.
A signal on the D INPUT is transfered to the Q
OUTPUT during the positive going transition of
the clock pulse.
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC74M
74VHC74T
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications maintaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
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74VHC74 Даташит, Описание, Даташиты
74VHC74
INPUT EQUIVALENT CIRCUIT
TRUTH TABLE
CLR
L
H
L
H
H
H
X:Don’t Care
INPUTS
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
LOGIC DIAGRAMS
PIN DESCRIPTION
PIN No
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
S YM BO L
1CLR,
2CLR
1D, 2D
1CK, 2CK
1PR, 2PR
1Q, 2Q
1Q, 2Q
GND
VCC
NAME AND FUNCTION
Asyncronous Reset -
Direct Input
Data Input
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
Asyncronous Set - Direct
Input
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
Ground (0V)
Positive Supply Voltage
OUT PUT S
CK Q
Q
XLH
XH L
XHH
LH
HL
Qn Qn
F UNCTION
CLEAR
PRESET
NO CHANGE
Thislogic diagram has notbe used to estimate propagation delays
2/10







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74VHC74 Даташит, Описание, Даташиты
74VHC74
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC Supply Voltage
-0.5 to +7.0
V
VI DC Input Voltage
-0.5 to +7.0
V
VO DC Output Voltage
-0.5 to VCC + 0.5
V
IIK DC Input Diode Current
- 20 mA
IOK DC Output Diode Current
± 20 mA
IO DC Output Current
± 25 mA
ICC or IGND DC VCC or Ground Current
± 50 mA
Tstg Storage Temperature
-65 to +150
oC
TL Lead Temperature (10 sec)
300 oC
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC Supply Voltage
VI Input Voltage
VO Output Voltage
Top Operating Temperature
dt/dv Input Rise and Fall Time (see note 1) (VCC = 3.3 ± 0.3V)
(V CC = 5.0 ± 0.5V)
1) VIN from 30% to70%of VCC
Valu e
2.0 to 5.5
0 to 5.5
0 to VCC
-40 to +85
0 to 100
0 to 20
Unit
V
V
V
oC
ns/V
ns/V
DC SPECIFICATIONS
Symb ol
Parameter
VIH High Level Input
Voltage
VIL Low Level Input
Voltage
VOH High Level Output
Voltage
VOL Low Level Output
Voltage
II Input Leakage Current
ICC Quiescent Supply
Current
Test Conditions
V CC
( V)
2 .0
3.0 to 5.5
2.0
3.0 to 5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4 .5
3.0
4.5
0 to 5.5
5.5
IO=-50 µA
IO=-50 µA
IO=-50 µA
IO=-4 mA
IO=-8 mA
IO=50 µA
IO=50 µA
IO=50 µA
IO=4 mA
IO=8 mA
VI = 5.5V or GND
VI = VCC or GND
Value
TA = 25 oC
Min. Typ. Max.
-40 to 85 oC
Min . Max.
1.5 1.5
0.7VCC
0.7VCC
0.5 0.5
0.3VCC
0.3VCC
1.9 2.0
1.9
2.9 3.0
2.9
4.4 4.5
4.4
2.58 2.48
3.94 3.8
0.0 0.1
0.1
0.0 0.1
0.1
0.0 0.1
0.1
0.36 0.44
0.36 0.44
±0.1 ±1.0
2 20
Un it
V
V
V
V
µA
µA
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