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74VHCT573 PDF даташит

Спецификация 74VHCT573 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Octal D-Type Latch with 3-STATE Outputs».

Детали детали

Номер произв 74VHCT573
Описание Octal D-Type Latch with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VHCT573 Даташит, Описание, Даташиты
January 1998
Revised April 1999
74VHCT573A
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT573A is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a Latch Enable input (LE) and an Out-
put Enable input (OE). When the OE input is HIGH, the
eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-State.
Features
s High speed: tPD = 7.7 ns (typ) at TA = 25°C
s High Noise Immunity: VIH = 2.0V, VIL = 0.8V
s Power Down Protection is provided on all inputs and
outputs
s Low Noise: VOLP = 1.6V (max)
s Low Power Dissipation:
ICC = 4 µA (max) @ TA = 25°C
s Pin and function compatible with 74HCT573
Ordering Code:
Order Number Package Number
Package Description
74VHCT573AM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHCT573ASJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT573AMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT573AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS500028.prf
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74VHCT573 Даташит, Описание, Даташиты
Functional Description
The VHCT573A contains eight D-type latches with 3-
STATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs, a setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers
are enabled. When OE is HIGH the buffers are in the high
impedance mode, but, this does not interfere with entering
new data into the latches.
Truth Table
Inputs
OE LE
LH
LH
LL
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
D On
HH
LL
X O0
XZ
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHCT573 Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
(Note 3)
(Note 4)
Input Diode Current (IIK)
Output Diode Current (IOK) (Note 5)
DC Output Current (IOUT)
DC VCC/GND Current (ICC)
Storage Temperature (TSTG)
Lead Temperature (TL)
(Soldering, 10 seconds)
0.5V to +7.0V
0.5V to +7.0V
0.5V to VCC + 0.5V
0.5V to +7.0V
20 mA
±20 mA
±25 mA
±75 mA
65°C to +150°C
260°C
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC)
Input Voltage (VIN)
Output Voltage (VOUT)
(Note 3)
(Note 4)
4.5V to +5.5V
0V to +5.5V
0V to VCC
0V to 5.5V
Operating Temperature (TOPR)
40°C to +85°C
Input Rise and Fall Time (tr, tf)
VCC = 5.0V ± 0.5V
0 ns/V 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3: HIGH or LOW state. IOUT absolute maximum rating must be
observed.
Note 4: When outputs are in OFF-State or when VCC = OV.
Note 5: VOUT < GND, VOUT > VCC (Outputs Active).
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
IOZ
IIN
ICC
ICCT
Parameter
VCC
(V)
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
3-STATE Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
Maximum ICC/Input
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
5.5
0 5.5
5.5
5.5
IOFF
Output Leakage Current
0.0
(Power Down State)
Noise Characteristics
Min
2.0
2.0
4.40
3.94
Symbol
Parameter
VOLP
(Note 7)
Quiet Output Maximum Dynamic VOL
VOLV
(Note 7)
Quiet Output Minimum Dynamic VOL
VIHD
(Note 7)
Minimum HIGH Level Dynamic Input Voltage
VILD
(Note 7)
Maximum LOW Level Dynamic Input Voltage
Note 7: Parameter guaranteed by design.
TA = 25°C
Typ
Max
0.8
0.8
4.50
0.0 0.1
0.36
±0.25
±0.1
4.0
1.35
0.5
TA = −40°C to +85°C
Units
Min Max
Conditions
2.0
V
2.0
0.8
V
0.8
4.40
3.80
0.1
0.44
±2.5
±1.0
40.0
1.50
5.0
V VIN = VIH IOH = −50 µA
V or VIL IOH = −8 mA
V VIN = VIH IOL = 50 µA
V or VIL IOL = 8 mA
µA VIN = VIH or VIL
VOUT = VCC or GND
µA VIN = 5.5V or GND
µA VIN = VCC or GND
mA VIN = 3.4V
Other Inputs = VCC or GND
µA VOUT = 5.5V
VCC
TA = 25°C
Units
(V) Typ Limits
Conditions
5.0 1.2 1.6
V CL = 50 pF
5.0
1.2
1.6
V CL = 50 pF
5.0 2.0 V CL = 50 pF
5.0 0.8 V CL = 50 pF
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