74VHCT74A PDF даташит
Спецификация 74VHCT74A изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Dual D-Type Flip-Flop with Preset and Clear». |
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Детали детали
Номер произв | 74VHCT74A |
Описание | Dual D-Type Flip-Flop with Preset and Clear |
Производители | Fairchild Semiconductor |
логотип |
9 Pages
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May 2008
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
Features
n High speed: fMAX = 160MHz (Typ.) at TA = 25°C
n High noise immunity: VIH = 2.0V, VIL = 0.8V
n Power down protection is provided on all inputs and
outputs
n Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
n Pin and function compatible with 74HCT74
General Description
The VHCT74A is an advanced high speed CMOS Dual
D-Type Flip-Flop fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The signal level applied to
the D INPUT is transferred to the Q OUTPUT during the
positive going transition of the CK pulse. CLR and PR
are independent of the CK and are accomplished by set-
ting the appropriate input LOW.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with VCC = 0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V
to 5V systems and two supply systems such as battery
backup.
Ordering Information
Order Number
Package
Number
Package Description
74VHCT74AM
74VHCT74ASJ
74VHCT74AMTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
www.fairchildsemi.com
No Preview Available ! |
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
D1, D2
CK1, CK2
CLR1, CLR2
PR1, PR2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Outputs
Truth Table
Inputs
Outputs
CLR PR D CK Q Q Function
L H X X L H Clear
H L X X H L Preset
L LX X HH
H HL
LH
H HH
HL
H HX
Qn Qn No Change
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
2
www.fairchildsemi.com
No Preview Available ! |
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
TSTG
TL
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
Note 1
Note 2
Input Diode Current
Output Diode Current(3)
DC Output Current
DC VCC / GND Current
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to VCC + 0.5V
–0.5V to 7.0V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Recommended Operating Conditions(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC
VIN
VOUT
Supply Voltage
Input Voltage
Output Voltage
Note 1
Note 2
TOPR
tr, tf
Operating Temperature
Input Rise and Fall Time
VCC = 5.0V ±0.5V
Notes:
1. HIGH or LOW state. IOUT absolute maximum rating must be observed.
2. VCC = 0V.
3. VOUT < GND, VOUT > VCC (Outputs Active).
4. Unused inputs must be held HIGH or LOW. They may not float.
Rating
4.5V to +5.5V
0V to +5.5V
0V to VCC
0V to 5.5V
–40°C to +85°C
0ns/V ∼ 20ns/V
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
3
www.fairchildsemi.com
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