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74VHCT74AM PDF даташит

Спецификация 74VHCT74AM изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Dual D-Type Flip-Flop with Preset and Clear».

Детали детали

Номер произв 74VHCT74AM
Описание Dual D-Type Flip-Flop with Preset and Clear
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74VHCT74AM Даташит, Описание, Даташиты
July 1997
Revised April 1999
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHCT74A is an advanced high speed CMOS Dual D-
Type Flip-Flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The signal level applied to the D INPUT
is transferred to the Q OUTPUT during the positive going
transition of the CK pulse. CLR and PR are independent of
the CK and are accomplished by setting the appropriate
input LOW.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with VCC = 0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Features
s High speed: fMAX = 160 MHz (typ) at TA = 25°C
s High noise immunity: VIH = 2.0V, VIL = 0.8V
s Power down protection is provided on all inputs and
outputs
s Low power dissipation:
ICC = 2 µA (max) at TA = 25°C
s Pin and function compatible with 74HCT74
Ordering Code:
Order Number Package Number
Package Description
74VHCT74AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHCT74ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT74AMTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D1, D2
CK1, CK2
CLR1, CLR2
PR1, PR2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Outputs
Truth Table
Inputs
Outputs
Function
CLR PR D CK Q Q
L H X X L H Clear
H L X X H L Preset
L LX X HH
H H L
LH
H H H
HL
H H X
Qn Qn No
Change
© 1999 Fairchild Semiconductor Corporation DS500026.prf
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74VHCT74AM Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
(Note 2)
(Note 3)
Input Diode Current (IIK)
Output Diode Current (IOK)
(Note 4)
DC Output Current (IOUT)
DC VCC/GND Current (ICC)
Storage Temperature (TSTG)
Lead Temperature (TL)
Soldering (10 seconds)
0.5V to +7.0V
0.5V to +7.0V
0.5V to VCC + 0.5V
0.5V to 7.0V
20 mA
±20 mA
±25 mA
±50 mA
65°C to +150°C
260°C
Recommended Operating
Conditions (Note 5)
Supply Voltage (VCC)
Input Voltage (VIN)
Output Voltage (VOUT)
(Note 2)
(Note 3)
4.5V to 5.5V
0V to +5.5V
0V to VCC
0V to 5.5V
Operating Temperature (TOPR)
40°C to +85°C
Input Rise and Fall Time (tr, tf)
VCC = 5.0V ± 0.5V
0 ns/V 20 ns/V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: HIGH or LOW state. IOUT absolute maximum rating must be
observed.
Note 3: VCC = 0V.
Note 4: VOUT < GND, VOUT > VCC.(Outputs Active)
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
IIN
ICC
ICCT
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
Maximum ICC/Input
VCC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
0–5.5
5.5
5.5
IOFF
Output Leakage Current
0.0
(Power Down State)
Min
2.0
2.0
4.40
3.94
TA = 25°C
Typ
4.50
0.0
Max
0.8
0.8
0.1
0.36
±0.1
2.0
1.35
+0.5
TA = −40°C to +85°C Units
Min Max
Conditions
2.0
V
2.0
0.8
V
0.8
4.40
3.80
0.1
0.44
±1.0
20.0
1.50
+5.0
V VIN = VIH IOH = −50 µA
or VIL IOH = −8 mA
V VIN = VIH IOL = 50 µA
or VIL IOL = 8 mA
µA VIN = 5.5V or GND
µA VIN = VCC or GND
mA VIN = 3.4V
Other Inputs = VCC or GND
µA VOUT = 5.5V
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74VHCT74AM Даташит, Описание, Даташиты
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = 25°C
TA = −40°C to +85°C
(V)
(Note 6)
Min
Typ
Max
Min
Max
Units
Conditions
fMAX
tPLH
tPHL
Maximum Clock
Frequency
Propagation Delay Time
(CK-Q, Q)
5.0 100
5.0 80
160
140
80 MHz CL = 15 pF
65 CL = 50 pF
5.0 5.8 7.8 1.0 9.0 ns CL = 15 pF
5.0
6.3 8.8 1.0 10.0
CL = 50 pF
tPLH Propagation Delay time
tPHL (CLR, PR -Q, Q)
5.0
5.0
7.6
10.4
1.0
12.0
ns CL = 15 pF
8.1 11.4 1.0 13.0
CL = 50 pF
CIN Input Capacitance
4 10
10 pF VCC = Open
CPD Power Dissipation Capacitance
24
pF (Note 7)
Note 6: VCC is 5.0 ± 0.5V
Note 7: CPD is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr) = CPD × VCC × fIN + ICC/2 (per flip-flop).
AC Operating Requirements
Symbol
Parameter
tW(L)
tW(H)
tW(L)
tS
tH
tREM
Minimum Pulse Width (CK)
Minimum Pulse Width
(CLR, PR)
Minimum Setup Time
Minimum Hold Time
Minimum Removal Time
(CLR, PR)
VCC
(V)
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
TA = 25°C
TA = −40°C to +85°C
Typ Guaranteed Minimum
5.0 5.0
Units
ns
5.0 5.0 ns
5.0 5.0 ns
0 0 ns
3.5 3.5 ns
3 www.fairchildsemi.com










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