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PDF 74HC595 Data sheet ( Hoja de datos )
| Número de pieza | 74HC595 | |
| Descripción | 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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 1. 8-Bit Shift Registers - TI  Hay una vista previa y un enlace de descarga de 74HC595 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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74HC595
8−Bit Serial−Input/Serial or
Parallel−Output Shift
Register with Latched
3−State Outputs
High−Performance Silicon−Gate CMOS
The 74HC595 consists of an 8−bit shift register and an 8−bit D−type
latch with three−state parallel outputs. The shift register accepts serial
data and provides a serial output. The shift register also provides
parallel data to the 8−bit latch. The shift register and latch have
independent clock inputs. This device also has an asynchronous reset
for the shift register.
The HC595 directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
− Improved Propagation Delays
− 50% Lower Quiescent Power
− Improved Input Noise and Latchup Immunity
• These are Pb−Free Devices
16
1
16
1
http://onsemi.com
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
HC595G
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HC
595
ALYW G
G
1
HC595 = Device Code
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1
Publication Order Number:
74HC595/D
1 page  
74HC595
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
(V)
Guaranteed Limit
– 55 to 25_C v 85_C v 125_C
Unit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0 6.0
3.0 15
4.5 30
6.0 35
4.8 4.0 MHz
10 8.0
24 20
28 24
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
2.0 140
3.0 100
4.5 28
6.0 24
175 210 ns
125 150
35 42
30 36
tPHL Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
2.0 145
3.0 100
4.5 29
6.0 25
180 220 ns
125 150
36 44
31 38
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA − QH
(Figures 3 and 7)
2.0 140
3.0 100
4.5 28
6.0 24
175 210 ns
125 150
35 42
30 36
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0 150
3.0 100
4.5 30
6.0 26
190 225 ns
125 150
38 45
33 38
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0 135
3.0 90
4.5 27
6.0 23
170 205 ns
110 130
34 41
29 35
tTLH,
tTHL
Maximum Output Transition Time, QA − QH
(Figures 3 and 7)
2.0 60
3.0 23
4.5 12
6.0 10
75 90 ns
27 31
15 18
13 15
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
16 19
Cin Maximum Input Capacitance
− 10
10 10 pF
Cout Maximum Three−State Output Capacitance (Output in
High−Impedance State), QA − QH
− 15
15 15 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Package)*
300 pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
5
5 Page 
74HC595
PACKAGE DIMENSIONS
−A−
16
1
SOIC−16
CASE 751B−05
ISSUE K
9
−B− P 8 PL
8 0.25 (0.010) M B S
G
−T− SEATING
PLANE
K
C
D 16 PL
0.25 (0.010) M T B S A S
R X 45_
F
MJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
SOLDERING FOOTPRINT*
8X
6.40
16X 1.12
1 16
16X
0.58
1.27
PITCH
89
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 74HC595.PDF ] | |
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