|
|
PDF 7C187-35 Data sheet ( Hoja de datos )
| Número de pieza | 7C187-35 | |
| Descripción | 64K x 1 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 7C187-35 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
87
CY7C187
Features
• High speed
— 15 ns
• CMOS for optimum speed/power
• Low active power
— 495 mW
• Low standby power
— 220 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C187 is a high-performance CMOS static RAM orga-
nized as 65,536 words x 1 bit. Easy memory expansion is pro-
64K x 1 Static RAM
vided by an active LOW Chip Enable (CE) and three-state driv-
ers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A15).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied on the address pin will appear on the data output (DOUT)
pin.
The output pin stays in high-impedance state when Chip En-
able (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C187 utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
INPUT BUFFER
A12
A13
A14
A15 256 x 256
A0 ARRAY
A1
A2
A3
COLUMN DECODER
POWER
DOWN
Selection Guide[1]
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Note:
1. For military specifications, see the CY7C187A datasheet.
DI
DO
CE
SOJ
Top View
A0
A1
A2
A3
A4
A5
NC
A6
A7
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 A15
22 A14
21 A13
20 A12
19 NC
18 A11
17 A10
16 A9
15 A8
14 DIN
13 CE
C187–3
WE
C187–1
DIP
Top View
A0
A1
A2
A3
A4
A5
A6
A7
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
22 VCC
21 A15
20 A14
19 A13
18 A12
17 A11
16 A10
15 A9
14 A8
13 DIN
12 CE
C187–2
7C187-15
15
90
40/20
7C187-20
20
80
40/20
7C187-25
25
70
20/20
7C187-35
35
70
20/20
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05044 Rev. **
Revised August 24, 2001
1 page  
CY7C187
Switching Waveforms
Read Cycle No. 2[10, 12]
CE
DATA OUT
tACE
tLZCE
HIGH IMPEDANCE
tRC
DATA VALID
tHZCE
HIGH
IMPEDANCE
VCC
SUPPLY
CURRENT
tPU
50%
tPD
50%
Write Cycle No. 1 (WE Controlled)[11]
ADDRESS
CE
WE
DATA IN
tSA
tWC
tSCE
tAW
tPWE
tSD
DATA VALID
tHA
tHD
DATA OUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH IMPEDANCE
Write Cycle No. 2 (CE Controlled)[11, 13]
ADDRESS
CE
tSA
WE
tWC
tSCE
tAW
tPWE
tHA
ICC
ISB
C187–7
C187–8
DATA IN
tSD
DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
C187–9
Document #: 38-05044 Rev. **
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 7C187-35.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 7C187-35 | 64K x 1 Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |