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7C256 PDF даташит

Спецификация 7C256 изготовлена ​​​​«ETC» и имеет функцию, называемую «High Performance 32Kx8 CMOS SRAM».

Детали детали

Номер произв 7C256
Описание High Performance 32Kx8 CMOS SRAM
Производители ETC
логотип ETC логотип 

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7C256 Даташит, Описание, Даташиты
High Performance
32K×8
CMOS SRAM
32K×8 CMOS SRAM (Common I/O)
AS7C256
AS7C256L
FEATURES
• Organization: 32,768 words × 8 bits
• High speed
– 10/12/15/20/25/35 ns address access time
– 3/3/4/5/6/8 ns output enable access time
• Low power consumption
– Active: 660 mW max (10 ns cycle)
– Standby: 11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version
– Very low DC component in active power
• 2.0V data retention (L version)
• Equal access and cycle times
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
– 300 mil PDIP and SOJ
Socket compatible with 7C512 and 7C1024
– 330 mil SOIC
– 8×13.4 TSOP
• ESD protection > 2000 volts
• Latch-up current > 200 mA
LOGIC BLOCK DIAGRAM
PIN ARRANGEMENT
Vcc
GND
A0
A1
A2
A3
A4
A5
A6
A14
INPUT BUFFER
256×128×8
ARRAY
(262,144)
I/O7
I/O0
COLUMN DECODER
AAAAAAA
7 8 9 10 11 12 13
CONTROL
CIRCUIT
WE
OE
CE
SELECTION GUIDE
AS7C256-01
DIP, SOJ, SOIC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
TSOP 8×13.4
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
1 28 Vcc
2 27 WE
3 26 A13
4 25 A8
5 24 A9
6 23 A11
7 22 OE
8 21 A10
9 20 CE
10 19 I/O7
11 18 I/O6
12 17 I/O5
13 16 I/O4
14 15 I/O3
AS7C256
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A0 AS7C256-02
9 A1
8 A2
Maximum Address Access Time
Maximum Output Enable Access Time
Maximum Operating Current
Maximum CMOS Standby Current
L
7C256-10 7C256-12 7C256-15 7C256-20 7C256-25 7C256-35 Unit
10 12 15 20 25 35 ns
3 3 4 5 6 8 ns
120 115 110 100 90 80 mA
2.0 2.0 2.0 2.0 2.0 2.0 mA
0.5 0.5 0.5 0.5 0.5 0.5 mA
ALLIANCE SEMICONDUCTOR









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7C256 Даташит, Описание, Даташиты
AS7C256
AS7C256L
FUNCTIONAL DESCRIPTION
The AS7C256 is a high performance CMOS 262,144-bit
Static Random Access Memory (SRAM) organized as
32,768 words × 8 bits. It is designed for memory applica-
tions where fast data access, low power, and simple interfac-
ing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of
10/12/15/20/25/35 ns with output enable access times (tOE)
of 3/3/4/5/6/8 ns are ideal for high performance applica-
tions. A chip enable (CE) input permits easy memory
expansion with multiple-bank memory organizations.
When CE is HIGH the device enters standby mode. The
standard AS7C256 is guaranteed not to exceed 11 mW
power consumption in standby mode; the L version is guar-
anteed not to exceed 2.75 mW, and typically requires only
500 µW. The L version also offers 2.0V data retention, with
maximum power consumption in this mode of 300 µW.
A write cycle is accomplished by asserting chip enable (CE)
and write enable (WE) LOW. Data on the input pins
I/O0-I/O7 is written on the rising edge of WE (write cycle 1)
or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE)
and output enable (OE) LOW, with write enable (WE)
HIGH. The chip drives I/O pins with the data word refer-
enced by the input address. When chip enable or output
enable is HIGH, or write enable is LOW, output drivers stay
in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and opera-
tion is from a single 5V supply. The AS7C256 is packaged
in all high volume industry standard packages.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol Min
Max
Unit
Voltage on Any Pin Relative to GND
Vt –0.5 +7.0 V
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
PD
Tstg
Tbias
–55
–10
1.0
+150
+85
W
oC
oC
DC Output Current
Iout
20 mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
.
TRUTH TABLE
CE WE OE
HXX
L HH
L HL
LLX
Key: X = Don’t Care, L = LOW, H = HIGH
Data
High Z
High Z
Dout
Din
Mode
Standby (ISB, ISB1)
Output Disable
Read
Write
2









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7C256 Даташит, Описание, Даташиты
AS7C256
AS7C256L
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input Voltage
*VIL min = –3.0V for pulse width less than tRC/2.
Symbol
VCC
GND
VIH
VIL
Min
4.5
0.0
2.2
–0.5*
Typ
5.0
0.0
(Ta = 0°C to +70°C)
Max
5.5
0.0
VCC+1
0.8
Unit
V
V
V
V
DC OPERATING CHARACTERISTICS1
(VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)
Parameter
Symbol Test Conditions
Input Leakage
Current
Output Leakage
Current
|ILI|
|ILO|
Operating Power
Supply Current
ICC
VCC = Max,
Vin = GND to VCC
CE = VIH, VCC = Max,
Vout = GND to VCC
CE = VIL, f = fmax,
Iout = 0 mA
Standby
Power Supply
Current
ISB
ISB1
Output Voltage
VOL
VOH
CE = VIH, f = fmax
CE > VCC–0.2V, f = 0,
Vin 0.2V or
Vin VCC–0.2V
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
-10 -12 -15 -20 -25 -35
Min Max Min Max Min Max Min Max Min Max Min Max Unit
– 1 – 1 – 1 – 1 – 1 – 1 µA
– 1 – 1 – 1 – 1 – 1 – 1 µA
– 120 – 115 – 110 – 100 – 90 – 80 mA
L – 115 – 110 – 105 – 95 – 85 – 75 mA
– 45 – 40 – 30 – 30 – 25 – 25 mA
L – 40 – 35 – 25 – 25 – 20 – 20 mA
– 2.0 – 2.0 – 2.0 – 2.0 – 2.0 – 2.0 mA
L – 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – 0.5 mA
– 0.4 – 0.4 – 0.4 – 0.4 – 0.4 – 0.4 V
2.4 – 2.4 – 2.4 – 2.4 – 2.4 – 2.4 – V
CAPACITANCE2
Parameter
Input Capacitance
I/O Capacitance
Symbol
CIN
CI/O
(f = 1 MHz, Ta = Room Temperature, VCC = 5V)
Signals
A, CE, WE, OE
I/O
Test Conditions
Vin = 0V
Vin = Vout = 0V
Max
5
7
Unit
pF
pF
3










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Номер в каталогеОписаниеПроизводители
7C256High Performance 32Kx8 CMOS SRAMETC
ETC
7C256-10High Performance 32Kx8 CMOS SRAMETC
ETC
7C256-12High Performance 32Kx8 CMOS SRAMETC
ETC
7C256-15High Performance 32Kx8 CMOS SRAMETC
ETC

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