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PDF MAX149 Data sheet ( Hoja de datos )
| Número de pieza | MAX149 | |
| Descripción | +2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-0464; Rev 5; 1/12
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
General Description
The MAX148/MAX149 10-bit data-acquisition systems
combine an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from a
single +2.7V to +5.25V supply, and sample to 133ksps.
Both devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI/
QSPIK and MICROWIREK devices without external
logic. A serial-strobe output allows direct connection to
TMS320-family digital signal processors. The MAX148/
MAX149 use either the internal clock or an external seri-
al-interface clock to perform successive-approximation
analog-to-digital conversions.
The MAX149 has an internal 2.5V reference, while the
MAX148 requires an external reference. Both parts
have a reference-buffer amplifier with a Q1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDN pin and
a software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface automatically
powers up the MAX148/MAX149, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60FA at reduced sampling rates.
The MAX148/MAX149 are available in 20-pin PDIP and
20-pin SSOP packages.
For 4-channel versions of these devices, see the
MAX1248/MAX1249 data sheet.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Pin Configuration appears at end of data sheet.
Features
S 8-Channel Single-Ended or 4-Channel Differential
Inputs
S Single-Supply Operation: +2.7V to +5.25V
S Internal 2.5V Reference (MAX149)
S Low Power: 1.2mA (133ksps, 3V Supply)
54µA (1ksps, 3V Supply)
1µA (Power-Down Mode)
S SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
S Software-Configurable Unipolar or Bipolar Inputs
S 20-Pin DIP/SSOP Packages
Ordering Information
PART†
MAX148ACPP+
MAX148BCPP+
MAX148ACAP+
MAX148BCAP+
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-
PACKAGE
20 PDIP
20 PDIP
20 SSOP
20 SSOP
INL
(LSB)
±1/2
±1
±1/2
±1
Ordering Information continued at end of data sheet.
†Contact factory for availability of alternate surface-mount
package.
+Denotes a lead(Pb)-free/RoHS-compliant package.
O TO
+2.5V
ANALOG
INPUTS
4.7FF
0.01FF
Typical Operating Circuit
+3V
CH0 VDD
VDD
0.1FF
DGND
MAX149
CH7 AGND
VREF COM
READJ
CS
SCLK
DIN
DOUT
SSTRB
SHDN
CPU
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
QSPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
1 page  
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SYMBOL
CONDITIONS
tACQ
tDS
tDH
tDO Figure 1, MAX14_ _C/E
tDV Figure 1
tTR Figure 2
tCSS
tCSH
tCH
tCL
tSSTRB Figure 1
tSDV External clock mode only, Figure 1
tSTR External clock mode only, Figure 2
tSCK Internal clock mode only (Note 7)
MIN TYP MAX UNITS
1.5 μs
100 ns
0 ns
20 200 ns
240 ns
240 ns
100 ns
0 ns
200 ns
200 ns
240 ns
240 ns
240 ns
0 ns
Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300FVP-P.
Note 10: Guaranteed by design. Not subject to production testing.
Note 11: The MAX148 typically draws 400FA less than the values shown.
Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|.
5
5 Page 
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Table 3. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CH0
+
-
CH1
-
+
CH2
+
-
CH3
-
+
CH4
+
-
CH5
-
+
CH6
+
-
CH7
-
+
CS
SCLK
1
tACQ
48
12 16
20 24
DIN
SSTRB
DOUT
A/D STATE
SEL2 SEL1 SEL0
UNI/ SGL/
BIP DIF
PD1
PD0
START
RB1
ACQUISITION
IDLE 1.5Fs
(fSCLK = 2MHz)
RB2 RB3
B9
MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
FILLED WITH
S0 ZEROS
CONVERSION
IDLE
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK P 2MHz)
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull CS
low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB3.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three
trailing zeros. The total conversion time is a function of
the serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120Fs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the fall-
ing edge of SCLK in MSB-first format.
Clock Modes
The MAX148/MAX149 may use either an external serial
clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the exter-
nal clock shifts data in and out of the MAX148/MAX149.
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MAX149.PDF ] | |
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