|
|
PDF 80960CA-25 Data sheet ( Hoja de datos )
| Número de pieza | 80960CA-25 | |
| Descripción | SPECIAL ENVIRONMENT 80960CA-25/ -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 80960CA-25 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
SPECIAL ENVIRONMENT 80960CA-25 -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
Two Instructions Clock Sustained Execution
Four 59 Mbytes s DMA Channels with Data Chaining
Demultiplexed 32-bit Burst Bus with Pipelining
Y 32-bit Parallel Architecture
Two Instructions clock Execution
Load Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulates 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model
Y Fast Procedure Call Return Model
Full Procedure Call in 4 Clocks
Y On-Chip Register Cache
Caches Registers on Call Ret
Minimum of 6 Frames Provided
Up to 15 Programmable Frames
Y On-Chip instruction Cache
1 Kbyte Two-Way Set Associative
128-bit Path to instruction Sequencer
Cache-Lock Modes
Cache-Off Mode
Y High Bandwidth On-Chip Data RAM
1 Kbyte On-Chip Data RAM
Sustains 128 bits per Clock Access
Y Four On-Chip DMA Channels
59 Mbytes s Fly-by Transfers
32 Mbytes s Two-Cycle Transfers
Data Chaining
Data Packing Unpacking
Programmable Priority Method
Y 32-Bit Demultiplexed Burst Bus
128-bit internal Data Paths to and
from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8- 16- or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin
Y Selectable Big or Little Endian Byte
Ordering
Y High-Speed Interrupt Controller
Up to 248 External interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four internal DMA Interrupts
Separate Non-maskable interrupt Pin
Context Switch in 750 ns Typical
Y Product Grades Available
SE3 b40 C to a110 C
December 1994
Order Number 271327-001
1 page  
www.DataSheet4U.com
SPECIAL ENVIRONMENT 80960CA-25 -16
1 0 PURPOSE
This document provides electrical characteristics for
the 25 and 16 MHz versions of the 80960CA For a
detailed description of any 80960CA functional
topic other than parametric performance consult
the 80960CA Product Overview (Order No 270669)
or the i960 CA Microprocessor User’s Manual (Or-
der No 270710) To obtain data sheet updates and
errata please call Intel’s FaxBACK data-on-de-
mand system (1-800-628-2283 or 916-356-3105)
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600)
2 0 80960CA OVERVIEW
The 80960CA is the second-generation member of
the 80960 family of embedded processors The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals and instruction set extensions to shift
64-bit operands and configure on-chip hardware
Multiple 128-bit internal buses on-chip instruction
caching and a sophisticated instruction scheduler al-
low the processor to sustain execution of two in-
structions every clock and peak at execution of
three instructions per clock
A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte s bandwidth to a system’s high-
speed external memory sub-system In addition the
80960CA’s on-chip caching of instructions proce-
dure context and critical program data substantially
decouple system performance from the wait states
associated with accesses to the system’s slower
cost sensitive main memory subsystem
The 80960CA bus controller integrates full wait state
and bus width control for highest system perform-
ance with minimal system design complexity Un-
aligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip DMA channels perform single-
cycle or two-cycle transfers data packing and un-
packing and data chaining Block transfers in addi-
tion to source or destination synchronized trans-
fers are provided
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (‘‘latency’’) time of
750 ns
Figure 1 80960CA Block Diagram
271327 – 1
5
5 Page 
www.DataSheet4U.com
SPECIAL ENVIRONMENT 80960CA-25 -16
Name
BOFF
HOLDA
BREQ
DC
DMA
SUP
Table 3 80960CA Pin Description External Bus Signals (Continued)
Type
I
S(L)
H(Z)
R(Z)
O
S
H(1)
R(Q)
O
S
H(Q)
R(0)
O
S
H(Z)
R(Z)
O
S
H(Z)
R(Z)
O
S
H(Z)
R(Z)
Description
BUS BACKOFF when asserted suspends the current access and causes
the bus pins to float When BOFF is deasserted the ADS signal is asserted
on the next clock cycle and the access is resumed
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has
relinquished control of the external bus When HOLDA is asserted the
external address bus data bus and bus control signals are floated HOLD
BOFF HOLDA and BREQ are used together to arbitrate access to the
processor’s external bus by external bus agents Since the processor grants
HOLD requests and enters the Hold Acknowledge state even while RESET is
asserted the state of the HOLDA pin is independent of the RESET pin
BUS REQUEST is asserted when the bus controller has a request pending
BREQ can be used by external bus arbitration logic in conjunction with HOLD
and HOLDA to determine when to return mastership of the external bus to the
processor
DATA OR CODE is asserted for a data request and deasserted for instruction
requests D C has the same timing as W R
DMA ACCESS indicates whether the bus request was initiated by the DMA
controller DMA is asserted for any DMA request DMA is deasserted for all
other requests
SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode SUP is asserted when the request has supervisor privileges
and is deasserted otherwise SUP can be used to isolate supervisor code and
data structures from non-supervisor requests
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 80960CA-25.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 80960CA-25 | SPECIAL ENVIRONMENT 80960CA-25/ -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR | Intel Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |